Re: RISC-V: quanta parte del processore ha licenza libera?
>>>>> "AR" == Alessandro Rubini <firstname.lastname@example.org> writes:
AR> riscv-spec-20191213.pdf pagina 23 (ricordavo bene):
AR> The conditional branches were designed to include arithmetic
AR> comparison operations between two registers (as also done in
AR> PA-RISC, Xtensa, and MIPS R6), rather than use condition codes
AR> (x86, ARM, SPARC, PowerPC), or to only compare one register
AR> against zero (Alpha, MIPS), or two registers only for equality
AR> (MIPS). This design was motivated by the observation that a
AR> combined compare-and-branch instruction fits into a regular
AR> pipeline, avoids additional condition code state or use of a
AR> temporary register, and reduces static code size and dynamic
AR> instruction fetch traffic. Another point is that comparisons
AR> against zero require non-trivial circuit delay (especially after
AR> the move to static logic in advanced processes) and so are almost
AR> as expensive as arithmetic magnitude compares. Another advantage
AR> of a fused compare-and-branch instruction is that branches are
AR> observed earlier in the front-end instruction stream, and so can
AR> be predicted earlier. There is perhaps an advantage to a design
AR> with condition codes in the case where multiple branches can be
AR> taken based on the same condition codes, but we believe this case
AR> to be relatively rare.
Lo so, non si fa, non si cita un grosso blocco di testo per un
commento di due righe...
Ma diamine, quanto mi mancava leggere cose del genere...
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