Re: RISC-V: quanta parte del processore ha licenza libera?

[Alessandro Rubini <rubini@arcana.linux.it>]

>> La differenza e` che riscV e` stato pensato tenendo in
>> considerazione tutta l'esperienza del settore, prendendo il meglio di
>> tutte le idee precedenti e scartando gli errori (per esempio, se
>> ricordo bene, non ha un registro "flags", e il manuale spiega
>> perche`).
> 
> Questa è interessante, dove la trovo?

riscv-spec-20191213.pdf pagina 23 (ricordavo bene):

   The conditional branches were designed to include arithmetic
   comparison operations between two registers (as also done in PA-RISC,
   Xtensa, and MIPS R6), rather than use condition codes (x86, ARM,
   SPARC, PowerPC), or to only compare one register against zero (Alpha,
   MIPS), or two registers only for equality (MIPS). This design was
   motivated by the observation that a combined compare-and-branch
   instruction fits into a regular pipeline, avoids additional condition
   code state or use of a temporary register, and reduces static code
   size and dynamic instruction fetch traffic. Another point is that
   comparisons against zero require non-trivial circuit delay (especially
   after the move to static logic in advanced processes) and so are
   almost as expensive as arithmetic magnitude compares. Another
   advantage of a fused compare-and-branch instruction is that branches
   are observed earlier in the front-end instruction stream, and so can
   be predicted earlier. There is perhaps an advantage to a design with
   condition codes in the case where multiple branches can be taken based
   on the same condition codes, but we believe this case to be relatively
   rare.

   [...]

saluti
/alessandro