Re: RISC-V: quanta parte del processore ha licenza libera?
> io lo vedo l'articolo, ma è davvero stringato
Ok, anch'io. Non lo chiamo articolo, per me e` l'occhiello del video.
> purtroppo io conosco poco di hardware e non ho capito cosa intendi per
> "rema contro".
Tutti sono entusiasti di risc-V perche` e` libero, mentre la tesi di
Andreas Speiss e` che la parte libera e` trascurabile sul totale e i
chip li trovi fatti dai soliti vendor che prendono un pezzo libero e
lo blindano nel loro mondo proprietario.
E` vero, ma non ci sono solo loro.
>> Inoltre riscV e` l'unica architettura gia` definita nella sua versione
>> a 128 bit.
>
> questo lo avevo visto e mi ero stupito... ma non avevo indagato oltre
Cito sotto.
> A 128-bit port is simply not realistic at this time.
> https://wiki.debian.org/RISC-V
Certo. Non e` un problema di risc-V, e` il mondo che non e` pronto.
Sull'idea di avere un 128 bit gia` definito, cito la specifica
dell'architettura:
Although 64-bit address spaces are a requirement for larger systems,
we believe 32-bit address spaces will remain adequate for many
embedded and client devices for decades to come and will be desirable
to lower memory traffic and energy consumption. In addition, 32-bit
address spaces are sufficient for educational purposes. A larger flat
128-bit address space might eventually be required, so we ensured this
could be accommodated within the RISC-V ISA framework.
E piu` avanti:
The primary reason to extend integer register width is to support
larger address spaces. It is not clear when a flat address space
larger than 64 bits will be required. At the time of writing, the
fastest supercomputer in the world as measured by the Top500 benchmark
had over 1 PB of DRAM, and would require over 50 bits of address space
if all the DRAM resided in a single address space. Some
warehouse-scale computers already contain even larger quantities of
DRAM, and new dense solid-state non-volatile memories and fast
interconnect technologies might drive a demand for even larger memory
spaces. Exascale systems research is targeting 100 PB memory systems,
which occupy 57 bits of address space. At historic rates of growth, it
is possible that greater than 64 bits of address space might be
required before 2030. History suggests that whenever it becomes clear
that more than 64 bits of address space is needed, architects will
repeat intensive debates about alternatives to extending the address
space, including segmentation, 96-bit address spaces, and software
workarounds, until, finally, flat 128- bit address spaces will be
adopted as the simplest and best solution. We have not frozen the
RV128 spec at this time, as there might be need to evolve the design
based on actual usage of 128-bit address spaces.
Non ho parole. Chapeau.
saluti
/alessandro
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