/* The Blizzard 2060 DMA interface
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Only two things can be programmed in the Blizzard DMA:
* 1) The data direction is controlled by the status of bit 31 (1 =
write)
* 2) The source/dest address (word aligned, shifted one right) in
bits 30-0
*
* Figure out interrupt status by reading the ESP status byte.
*/
struct blz2060_dma_registers {
volatile unsigned char dma_led_ctrl; /* DMA led control
[0x000] */
unsigned char dmapad1[0x0f];
volatile unsigned char dma_addr0; /* DMA address (MSB)
[0x010] */
unsigned char dmapad2[0x03];
volatile unsigned char dma_addr1; /* DMA address
[0x014] */
unsigned char dmapad3[0x03];
volatile unsigned char dma_addr2; /* DMA address
[0x018] */
unsigned char dmapad4[0x03];
volatile unsigned char dma_addr3; /* DMA address (LSB)
[0x01c] */
};