Re: Advice on system purchase
On 10/30/2012 11:58 AM, Celejar wrote:
> Just saw that, too:
Do note that the SeaMicro acquisition was announced in March. Before
the acquisition every SeaMicro product used Intel chips, from hot
running Xeons to low power Atoms.
AMD is reworking the entire product line from top to bottom replacing
the Intel chips, for the big obvious reason: they're Intel chips.
AMD does not have (although they could build) a chip comparable to the
Atom in performance/watt. The decision to use ARM to replace Atom is
not based on any "strategic vision" or epiphany. It's very simple:
"We can't use Atom any longer. What else is available with great
performance/watt, that's really cheap per chip? Duh, ARM."
That's exactly how the decision was made. Then they gave it to the
marketing folks who have done a great job on a few list members. ;)
> Although to be fair, Stan was talking about desktops, and this is about
If it ever gets off the ground. The super high density application
sever space within the sever market is small, specialized, and the
requirement for x86 pervasive. If this weren't true we'd already see 8
socket 32-way 1U ARM servers on the market, and we don't. We don't see
any ARM servers. I doubt AMD will sell many of the ARM based blades.
At some point AMD will drop the ARM idea. Then, if they smarten up,
they'll move the non-APU AthlonII x4 core to 32nm, bin sort and clock
down some chips to 1.6-2GHz to get TDP down to 20-25 watts--not as low
as Atom, but much more powerful. The rest they'll clock at 3.6-4.8GHz
(plus turbo) and sell them as faster version of the current non-APU AII x4.
Simultaneously they'll begin producing the Regor x2 core on the 32nm
process, bin sort and clock down units that can hit 10-15 watts at
1.6-2.4GHz, clock the rest at 3.8-5GHz (plus turbo) for sale as desktop
AthlonII x2 chips.
For those who are surely scratching heads about now, the reason for
using the no L3 Regor design vs the 4MB L3 Opteron HE "server processor"
or PhenomII x4 is power consumption vs performance. The 4MB L3 cache is
about 1/2 the transistor budget. Eliminating it saves ~50% on power
consumption and thus thermal output. And the applications typically run
on such mass "web" cluster systems don't tend to benefit significantly
But none of this will happen because AMD is running in panic mode with
the ATI acquisition being a financial failure, the stock tanking, and
the new CEO dreaming big ideas in an attempt to excite the analysts and