Re: SMP on 2xSM50?

[Joshua Uziel <uzi@uzix.org>]

* Marco Gaiarin <gaio@sv.lnf.it> [010221 03:10]:
> sv3:~# cat /proc/openprom/banner-name
> 'SPARCstation 10 (1 X 390Z55)'
> 
> No, it need more investigation... ;-)))
> [for now, i recompile kernel and try a reboot... ;-)))]

That's an SMx1 (x = {4,5,6,7,8}) processor... you've got one processor
(as evidenced by the "1 X 390Z55") and it's got the 1MB ecache as shown
by your "SuperCache" comment and the "Z55" (non-cache would be "Z50").

If you do a "module-info" at the OK prompt, you'll get input similar to
this:

        MBus  :  40 MHz
        SBus  :  20 MHz
        CPU#0 :  60 MHz SuperSPARC / SuperCache 3.1/3.3
        CPU#2 :  60 MHz SuperSPARC / SuperCache 3.1/3.3

In my case, I have a SM61's... 60MHz with 1MB ecache.