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Re: 7447A strange problem with MSR:POW (WAS: can't boot 2.6.17-rc1)

He's being sneaky - there's a copy of HID0 in the CR at this point from the caller, and bit 9 is the position for NAP.


On Apr 14, 2006, at 2:54 PM, Olof Johansson wrote:


On Fri, Apr 14, 2006 at 12:07:23PM -0700, Paul Mackerras wrote:
Becky Bruce writes:

Actually, I think the problem is that the code linux is using to turn on nap mode is not guaranteed to put the processor in nap mode by the
time the blr in ppc6xx_idle occurs.

Thanks, Becky.

This patch fixes it for me.  Comments, anyone?

The bf mnemonics had me scratching my head a while, it's not listed as
a simplified mnemonic in the 64-bit PEM. Two questions below.

+	tophys(r11, r1)		/* Make the idle task do a blr */
+	lwz	r9,_LINK(r11)
+	stw	r9,_NIP(r11)
 	mfspr	r11,SPRN_HID0
- rlwinm. r11,r11,0,10,8 /* Clear NAP & copy NAP bit !state to cr1 EQ */
-	cror	4*cr1+eq,4*cr0+eq,4*cr0+eq
+	rlwinm	r11,r11,0,10,8	/* Clear NAP */
 	rlwinm	r11,r11,0,9,7	/* Clear DOZE */
 	mtspr	SPRN_HID0, r11

 #ifdef DEBUG
-	beq	cr1,1f
+	bf	9,1f

Where is cr0 set now -- you took the dot off of rlwinm?

 	lis	r11,(nap_return_count-KERNELBASE)@ha
 	lwz	r9,nap_return_count@l(r11)
 	addi	r9,r9,1
 	stw	r9,nap_return_count@l(r11)
+#ifdef CONFIG_SMP
 	rlwinm	r9,r1,0,0,18
 	lwz	r11,TI_CPU(r9)
 	slwi	r11,r11,2
+	li	r11,0
 	/* Todo make sure all these are in the same page
-	 * and load r22 (@ha part + CPU offset) only once
+	 * and load r11 (@ha part + CPU offset) only once
-	beq	cr1,1f
+	bf	9,1f

Same comment as above w.r.t. cr0?


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