Re: Etch for ARM / Netwinder: where is NPTL support?
On Fri, May 11, 2007 at 02:58:39PM +0100, Martin Guy wrote:
> >> http://www.ertos.nicta.com.au/publications/papers/Wiggins_TUH_03.ps.gz.
> The paper has gone from its original location but is visible at
> http://martinwguy.co.uk/martin/Wiggins_TUH_03.ps.gz and
> entitled "Implementation of Fast Address-Space Switching
> and TLB Sharing on the StrongARM Processor". Only mentions StrongARM.
The paper defines a 'context switch' as a switch between threads of
execution in different address spaces. I.e., the definition of
'context switch' that the authors use does not include switching
between threads running in the same address space.
So when they say that a context switch requires a cache and TLB flush,
they are specifically _not_ saying that switching between threads
requires a cache flush and a TLB flush.
Yes, what the paper discusses is ways of mitigating the cost of
context switches, but again, using the definition of 'context switch'
of the authors, thread switches are not counted as context switches,
and the paper doesn't really talk about thread switching at all.
Re-read the very first line of the introduction, and then re-read