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Re: Etch for ARM / Netwinder: where is NPTL support?

> I can try and dig up the mail thread if that'll help
That would definitely help, please do.

I have the erudite:

Michael K Edwards 06/12/2006 Re: More ARM binutils fuckage

You wouldn't happen to have benchmarked a thread-intensive load o>n
your hardware with and without NPTL, would you?  I would expect the
gain to be significant from not blowing MMU context on every thread
switch, but I haven't seen hard numbers on ARM.

Why would LinuxThreads 'blow MMU context on every thread switch'?>

TLB and cache impacts of context switching on (some) ARMs are
discussed in

and seguito, and

2006/12/10, Ben Leslie <benno@ok-labs.com>:
I don't know the details of the implementation too well, but my understanding is:

1: LinuxThreads was user managed threads, so any thread switch did not
require a process switch, and was handled by user-level. Because of
this thread switch did not require a TLB flush or cache flush.

2: NTPL, every thread is a process. A process switch on ARM requires a
TLB and full cache flush due to the virtual caches on ARM. Unless NTPL
has some special logic to handle the case when it switches between two
threads in the same process it will be very expensive contexting
switching threads on a native Linux.[*]

Are these urban myths? Bugs long died and gone crumbly?


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