Re: success with ct65554
Taketoshi Sano wrote:
>
> Congratulations! I'm happy to hear that you got success.
>
> In <[🔎] 3A1460C3.62A35249@hecke.dartmouth.edu>,
> on "Thu, 16 Nov 2000 17:33:39 -0500", with "success with ct65554 ",
> "Thomas R. Shemanske" <trs@hecke.dartmouth.edu> wrote:
>
> trs> For the record, it seems unneccessary to use modelines, FPClock, or
> trs> DacSpeed. All of these options should be off. DacSpeed (if entered) is
> trs> ignored with the message:
> trs>
> trs> (WW) CHIPS(0): Option "DacSpeed" is not used.
>
> Can I make sure that you entered DacSpeed in this way ?
>
> Section "Device"
> Identifier "Generic Graphics Device"
> Driver "chips"
> DacSpeed 100.0
>
> "DacSpeed" should not follow "Option", so if you enter
>
> Section "Device"
> Identifier "Generic Graphics Device"
> Driver "chips"
> Option "DacSpeed" "100"
>
> then it would not work.
>
> The message "Option \"%s\" is not used\n" is written in common/xf86Option.c,
> but the DacSpeed [Option] should be handled by the code in common/xf86Config.c.
> (related codes are in parser/Device.c, where "case DACSPEED:" and "case OPTION"
> are parsed and handled differently).
>
> I think the former way should work, and if not, then there may be bug.
You are correct. I entered the DacSpeed as an option, so it was
ignored. The standard maximum DacSpeed (Pixel Clock) is 56.125 MHz and
the probed memory clock value is 40.090 MHz
The options below will work to produce 16bpp@1024x768 (with the
following specifications)
(--) CHIPS(0): Virtual size is 1024x768 (pitch 1024)
(**) CHIPS(0): Default mode "1024x768": 65.0 MHz, 48.4 kHz, 60.0 Hz
(**) CHIPS(0): Default mode "800x600": 56.3 MHz, 53.7 kHz, 85.1 Hz
(==) CHIPS(0): DPI set to (75, 75)
GetModeLine - scrn: 0 clock: 65000
GetModeLine - hdsp: 1024 hbeg: 1048 hend: 1184 httl: 1344
vdsp: 768 vbeg: 771 vend: 777 vttl: 806 flags: 10
***OPTIONS***
DacSpeed 65.0
# Option "SetMClk" "46.44 MHz" (that is, this option is commented
out).
or
# DacSpeed 65.0 (that is, this option is commented out)
Option "SetMClk" "46.44 MHz" .
or most likely some balance between the two. I am guessing changing the
pixel clock is the less risky?
Many thanks,
Tom
--
Thomas R. Shemanske
(Mailing Address) (Office/Internet Information)
Department of Mathematics 203 Choate House
6188 Bradley Hall thomas.r.shemanske@dartmouth.edu
Dartmouth College http://www.math.dartmouth.edu/~trs/
Hanover, NH 03755-3551 (603) 646 - 3179
Directions: http://www.math.dartmouth.edu/~trs/choatehouse.html
Office hours:
http://www.math.dartmouth.edu/~trs/frontmatter/office.html
Fall Term Office Hours: M, F: 2:30 - 4:00
Tu: 9:00 - 10:30
Reply to: