Re: memory question (hardware)
Latency, risk of failure, sure... also sheer design complexity (since you have
to solve the geometry of fitting more circuitry in the same space), and
subsequent complexity of fabrication (since you have to actually make
those tiny little circuits). There's also heat dissipation, which isn't so so
bad for memory but is still nontrivial.
Using smaller circuit paths means that the control signals wind up being
effectively "noisier" too (or so I understand), which affects a whole slew
of things, including memory timings among others.
At least this is all what I remember...!
On Sat, Jul 5, 2008 at 2:24 PM, Mag Gam <email@example.com> wrote:
> Thanks for the responses.
> What is the engineering challenge of having more memory in a single die? I expect latency would be a issue. Also, as Brad mentioned greater risk of failure.
> Any thing else?
> On Fri, Jul 4, 2008 at 11:04 AM, <firstname.lastname@example.org> wrote:
>> >---- Original Message ----
>> >From: email@example.com
>> >To: firstname.lastname@example.org
>> >Subject: RE: memory question (hardware)
>> >Date: Thu, 3 Jul 2008 01:08:10 -0400
>> >>I am curious...
>> >>When memory is manufactured why does a stick of 4GB memory cost 2.5
>> >times of
>> >>2GB memory? Is the manufacturing process that much different to
>> >justify the
>> Obviously we can't open up the sticks and look at the chips, but the
>> usual answer is that the 2G used "the older" technology and the 4G
>> used the "newer" technology and the chip vendor is trying to recoup
>> development costs. As the "newer" technology becomes the "older"
>> technology the cost will go down. With Moore's "law" this gives the
>> chip vendor about 18 months to recoup most of the development costs
>> and some profit.