Re: buildd failure for sparc - floating point encoding?

[Martin <inkubus@interalpha.co.uk>]

> > In short (IIRC) most modern SPARC processors implement 32 and 64 bit
> > IEEE floating point operations.
> All SPARCs, surely?
Not sure about some of the very obscure chips such as the ones used on
space craft.  Then again IIRC it's in the standards so without FP it
isn't really a SPARC chip.

> > This is the same as some MIPS processors (I suspect the SGi
> > setting), most PowerPCs (IBM-RS, Mac) and a host of other
> > architectures.
> The distinction is whether they're big or little endian.  Probably the
> majority of the architectures can actually be either.
Early MIPS chips had a pin to select which it would run as.  Most
architectures have some opcode to handle this sort of thing (even
inverse order loads) but I don't know of any other mainstream processors
that really do /both/.

That does make some sense given the DECStation 5000 is one of the few
examples of MIPS processors using the other endian set up,

> > x86 chips (and IIRC the Alpha) support 80 bit IEEE operations, which is
> > (I guess) why the have their own category.
> [I don't think that's true for Alpha.]
OTTOMH I'm not sure.  Had a feeling they did but without an Alpha or an
Alpha spec book I can't prove it.  Ofcourse this point is *way* OT.

> > If I was responsible for this code up stream I'd go for clarifying each
> > of these categories down to exactly what standard each one is rather
> > than what machines implement them.  But then again I'm pedantic like
> > that.
> As above, it's not pedantic.  Autoconf should be able to determine
> what the FP format is, though I don't think there's an existing test;
> it can definitely tell the byte sex.
I thought most folks did it at run time with fun with magic numbers et
al.

Cheers,
 - Martin

-- 
Martin
inkubus@interalpha.co.uk
"Seasons change, things come to pass"