problem booting up ultra sparc driven
> Hi,
> If sombody can help me to understand why my uldra sparc 1(driven) gets
> stuck before it start reading hard disks. I am attaching the log. I will
> really appriciate help
> -Regards
> -Badar
> Hardware Power ON
> Button Power ON
> Button Power ON
>
> @(#) Sun Ultra 1 SBus 3.0 Version 4 created 1995/11/26 17:47
> Probing keyboard Done
> %o0 = 0000.0000.0000.4001
>
> Executing Power On SelfTest
>
> 0>
>
> RESET SC Control=00000000
>
> 0>
>
> @(#)Sun Ultra 1 SBus POST 2.0.4 9/18/1995 03:59 PM
>
> 0>Date: 08/01 2002 18:11:57
>
> 0>Spitfire Version 2.2
>
> 0> SC id is 33403000 (UPA Number 3)
>
> 0>NVRAM Walking 0 and 1 Test
>
> 0>Probe, Test and Initialize Ecache
>
> 0> ECache RAM Size = 00080000
>
> 0> ECache TAG Size = 00002000
>
> 0>Running at Frequency 143 MHZ
>
> 0>Setting MC_Control1 to 0000026a
>
> 0>Setting MC_Control0 to 80000f28 (4,0)
>
> 0> SIMM Present Field 00000100
>
> 0>SIMM Pair Base Addr Low Size Hi Size Pair Status
>
> 0> 0 00000000.00000000 04000000 04000000 18
>
> 0>Running at Frequency 143 MHZ
>
> 0>Setting MC_Control1 to 0000026a
>
> 0>Setting MC_Control0 to 800001a2 (1,0)
>
> 0>UPA Cacheable Data and Check bit Bits
>
> 0>Stack Memory Test
>
> 0>SelfTest Initializing
>
> 0>EPROM Path Test
>
> 0> PROM Datapath Test
>
> 0>PROM Datapath Test PASSED
>
> 0>FPU Register Test
>
> 0> FSR Read/Write Test
>
> 0>FSR Read/Write Test PASSED
>
> 0>NVRAM Test
>
> 0>MMU Enable Test
>
> 0> DMMU Registers Access Test
>
> 0>DMMU Registers Access Test PASSED
>
> 0> DMMU TLB DATA RAM Access Test
>
> 0>DMMU TLB DATA RAM Access Test PASSED
>
> 0> DMMU TLB TAGS Access Test
>
> 0>DMMU TLB TAGS Access Test PASSED
>
> 0> IMMU Registers Access Test
>
> 0>IMMU Registers Access Test PASSED
>
> 0> IMMU TLB DATA RAM Access Test
>
> 0>IMMU TLB DATA RAM Access Test PASSED
>
> 0> IMMU TLB TAGS Access Test
>
> 0>IMMU TLB TAGS Access Test PASSED
>
> 0> DMMU Init
>
> 0>DMMU Init Test PASSED
>
> 0> IMMU Init
>
> 0>IMMU Init Test PASSED
>
> 0> I/D MMU TLB Load and Initialize
>
> 0>I/D MMU TLB Load and Initialize Test PASSED
>
> 0>Serial Ports Test
>
> 0> Serial Port Register Test
>
> 0>Serial Port Register Test PASSED
>
> 0> Serial Ports Test
>
> 0>Serial Ports Test PASSED
>
> 0>Ecache Test
>
> 0>Basic CPU Test
>
> 0> Instruction Cache Tag RAM Test
>
> 0>Instruction Cache Tag RAM Test PASSED
>
> 0> Instruction Cache Instruction RAM Test
>
> 0>Instruction Cache Instruction RAM Test PASSED
>
> 0> Instruction Cache Next Field RAM Test
>
> 0>Instruction Cache Next Field RAM Test PASSED
>
> 0> Instruction Cache Pre-decode RAM Test
>
> 0>Instruction Cache Pre-decode RAM Test PASSED
>
> 0> Data Cache RAM Test
>
> 0>Data Cache RAM Test PASSED
>
> 0> Data Cache Tags Test
>
> 0>Data Cache Tags Test PASSED
>
> 0>Memory Test
>
> 0> Memory Control Register Init
>
> 0>Running at Frequency 143 MHZ
>
> 0>Setting MC_Control1 to 0000026a
>
> 0>Setting MC_Control0 to 800001a2 (1,0)
>
> 0>Memory Control Register Init Test PASSED
>
> 0> Memory Clear Test
>
> 0>Memory Clear Test PASSED
>
> 0> Memory RAM (blk) Test
>
> 0>Memory RAM (blk) Test PASSED
>
> 0> Memory Address Line Test
>
> 0> Writing SIMM Pair 0 base address 00000000.00020000
>
> 0> Reading SIMM Pair 0 base address 00000000.00020000
>
> 0>Memory Address Line Test PASSED
>
> 0> Memory Stress Test
>
> 0>Memory Stress Test PASSED
>
> 0>FPU Functional Test
>
> 0> Floating Single Move Test
>
> 0>Floating Single Move Test PASSED
>
> 0> FPU Basic Operation Test
>
> 0>FPU Basic Operation Test PASSED
>
> 0>System Controller Test
>
> 0> SC Initialization
>
> 0> SC id is 33403000 (UPA Number 3)
>
> 0>SC Initialization Test PASSED
>
> 0>Caches and Coherency Test
>
> 0> Dcache Init
>
> 0>Dcache Init Test PASSED
>
> 0> Dcache Enable Test
>
> 0>Dcache Enable Test PASSED
>
> 0> Dcache Functionality Test
>
> 0>Dcache Functionality Test PASSED
>
> 0>SysIO Registers Test
>
> 0> SysIO Regsiter Initialization
>
> 0>SysIO Regsiter Initialization Test PASSED
>
> 0> IOMMU Registers and RAM Test
>
> 0>IOMMU Registers and RAM Test PASSED
>
> 0> Streaming Buffer Registers and RAM Test
>
> 0>Streaming Buffer Registers and RAM Test PASSED
>
> 0> SBus Control and Config Registers Test
>
> 0>SBus Control and Config Registers Test PASSED
>
> 0> SysIO RAM Initialization
>
> 0>SysIO RAM Initialization Test PASSED
>
> 0>CPU Functional Test
>
> 0> CPU Softint Registers and Interrupts Test
>
> 0>CPU Softint Registers and Interrupts Test PASSED
>
> 0> CPU Tick and Tick Compare Registers Test
>
> 0>CPU Tick and Tick Compare Registers Test PASSED
>
> 0> CPU Interrupt Registers and Dispatch Test
>
> 0>WARNING Test skipped, no alternate CPU
>
> 0>CPU Interrupt Registers and Dispatch Test PASSED
>
> 0> CPU Dispatch Control Register Test
>
> 0>CPU Dispatch Control Register Test PASSED
>
> 0>SysIO Functional Test
>
> 0> I/D MMU TLB Load and Initialize Test
>
> 0>I/D MMU TLB Load and Initialize Test PASSED
>
> 0> Clear Interrupt Map and State Registers
>
> 0>Clear Interrupt Map and State Registers Test PASSED
>
> 0> SysIO Interrupts Test
>
> 0>SysIO Interrupts Test PASSED
>
> 0> SysIO Timers/Counters Test
>
> 0>SysIO Timers/Counters Test PASSED
>
> 0> IOMMU Virtual Address TLB Tag Compare Test
>
> 0>IOMMU Virtual Address TLB Tag Compare Test PASSED
>
> 0> Streaming Buffer Flush Test
>
> 0>Streaming Buffer Flush Test PASSED
>
> 0> DMA Merge Buffer Test
>
> 0>DMA Merge Buffer Test PASSED
>
> 0>APC Test
>
> 0> APC Registers Tests Test
>
> 0>APC Registers Tests Test PASSED
>
> 0> APC DVMA Test
>
> 0>APC DVMA Test PASSED
>
> 0>I/D MMU Functional Test
>
> 0> I/D MMU TLB Load and Initialize Test
>
> 0>I/D MMU TLB Load and Initialize Test PASSED
>
> 0> Access Priviledged Data Page Test
>
> 0>Access Priviledged Data Page Test PASSED
>
> 0> Write to Protected Data Page Test
>
> 0>Write to Protected Data Page Test PASSED
>
> 0> Read/Write to Invalid Data Page Test
>
> 0>Read/Write to Invalid Data Page Test PASSED
>
> 0> Execute from Invalid Instr. Page Test
>
> 0>Execute from Invalid Instr. Page Test PASSED
>
> 0>Graphic Instructions Test
>
> 0>Data Cache Test
>
> 0> Dcache Init
>
> 0>Dcache Init Test PASSED
>
> 0> Dcache 256 Bytes Write then load Test
>
> 0>Dcache 256 Bytes Write then load Test PASSED
>
> 0> Dcache Enable Test
>
> 0>Dcache Enable Test PASSED
>
> 0>Instruction Cache Test
>
> 0> Icache Init
>
> 0>Icache Init Test PASSED
>
> 0> Icache Quick Test
>
> 0>Icache Quick Test PASSED
>
> 0>Forcing ECC Faults Test
>
> 0> ECC CE Pattern Test
>
> 0>ECC CE Pattern Test PASSED
>
> 0> ECC CE Check bit Test
>
> 0>ECC CE Check bit Test PASSED
>
> 0> ECC UE Pattern Test
>
> 0>ECC UE Pattern Test PASSED
>
> 0> ECC UE Check bit Test
>
> 0>ECC UE Check bit Test PASSED
>
> 0>Ecache Stress Test
>
> 0> Ecache Stress Test
>
> 0>Ecache Stress Test PASSED
>
> 0>Macio Test
>
> 0> MACIO Registers/RAM/FIFO Test
>
> 0>MACIO Registers/RAM/FIFO Test PASSED
>
> 0> Ethernet Registers Test
>
> 0>Ethernet Registers Test PASSED
>
> 0> Parallel Port Registers Test
>
> 0>Parallel Port Registers Test PASSED
>
> 0> MACIO SCSI DVMA Test
>
> 0>MACIO SCSI DVMA Test PASSED
>
> 0>POST PASSED. Remaining loops 0.
>
> Power On Selftest Completed
> Status = 0000.0000.0000.0000 ffff.ffff.f006.d268 0e66.0000.0180.1d0d
>
> Software Power ON
>
> @(#) Sun Ultra 1 SBus 3.0 Version 4 created 1995/11/26 17:47
> Clearing E$ Tags Done
> Clearing I/D TLBs Done
> Probing Memory Done
> MEM BASE = 0000.0000.0000.0000
> MEM SIZE = 0000.0000.0800.0000
> MMUs ON
> Copy Done
> PC = 0000.01ff.f000.1a6c
> PC = 0000.0000.0000.1ab0
> Decompressing into Memory Done
> Size = 0000.0000.0006.b6a0
> ttya initialized
> SC Control: EWP:0 IAP:0 FATAL:0 WAKEUP:0 BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
>
> Probing Memory Bank #0 64 + 64 : 128 Megab
> Probing Memory Bank #1 0 + 0 : 0 Megabytes
> Probing Memory Bank #2 0 + 0 : 0 Megabytes
> Probing Memory Bank #3 0 + 0 : 0 Megabytes
> Probing /sbus@1f,0 at 0,0 cgsix (VMSIZE:1M)
> Probing /sbus@1f,0 at 1,0 Nothing there
> Probing /sbus@1f,0 at 2,0 Nothing there(Its is stucked here not moving
> any where)
>
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