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Re: Altivec in baseline for ppc64?

crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Sun, Jul 18, 2021 at 4:17 AM Jeffrey Walton <noloader@gmail.com> wrote:

> I never really took notice that IBM captured the projects. But with
> your lens it sounds about right.
> ("Captured", as in regulatory capture as seen in the US. Regulatory
> capture is where private industry gets so cozy with government and
> regulators that industry writes their own rules and gov is just an
> extension of a few dominant players).

please do forgive my frustration at this particular strategic mistake:
i don't believe IBM intended for this to happen, it's more that there
simply wasn't anyone else around at the time to say "if you do
make this innocent-looking decision because it improves performance
for the *currently* only-existing hardware for the past 10 years - yours -
it's going to have consequences".

> Forgive my ignorance... Once traces of companies like NXP and IBM are
> removed, and Altivec is removed, what is left?

what has now been termed the "Scalar Fixed Point Compliancy Subset"
and the "Scalar Floating Point Compliancy Subset".  120 and 200
instructions or so, respectively.  they're in the v3.0C spec (1st few
pages) https://ftp.libre-soc.org/PowerISA_public.v3.0C.pdf and Henriok
and i updated the wikipedia page on Power ISA recently.

> Are some pieces of the ISA going to be (re)used?

yes, the entire scalar floating-point subset.  HOWEVER...
unnnforrrtunately, again: the assumption was "you'll always
have VSX", and as you're no doubt aware, FP <-> INT
conversion in Power ISA *used* to have move instructions
between FP and INT... but with VSX *assuming even integers
can be done in SIMD registers* those scalar FP<->INT MV
instructions were REMOVED somewhere around v2.06

so... we have to put in an RFP to put them back in, and at
the same time we intend to take the opportunity to propose
adding different *types* of conversion (java, javascript),
as well as "FP Load Immediate" using BF16 as the constant


> Or is the ISA being built from scratch?

hell no, that would be insane, you're no doubt aware how long
it took OpenRISC 1200 to fully mature.

in a nutshell, we're taking the scalar parts of the Power ISA, and
creating a "REP-like" repeater (with Vector context).  this multiplies
the base 200-ish instructions by between 1,000 and 8,000 to give
a total number of intrinsics somewhere well north of a quarter of
a million "options".  if you then bring in 3D Swizzle and other
advanced features that becomes several million.

all *WITHOUT* actually adding one single explicit Vector instruction
(as is normally done for Vector ISAs).

> Is it even PowerPC anymore?

yes - just very advanced.  or... more like: revival of 30+ year old
concepts and strapping JATO rockets to them.

> Is it just a RISC machine?

that's up to hardware micro-architects.  i'm designing Power ISA

> (PowerPC scatter/gather is quite lame, even in the latest ISA 3.0B, so
> I'm not sure there's much good stuff to reuse).

SVP64 is... comprehensive. https://libre-soc.org/openpower/sv/

but, bear in mind: SVP64 is micro-architecturally agnostic.  even an
Embedded system could implement some levels of it and get reduced
program size and reduced power consumption, rather than leverage
it for high performance.

> Anyway, I'm excited to see a SIMD alternative that could become
> mainstream.

Cray-style Vectors are seriously misunderstood. i cannot begin to
express how badly the entire computing industry has f***** up by
ignoring them. AVX-512 is a wake-up call: ARM SVE is a half-way
step in the right direction.

even the wikipedia page explicitly stated (until last month),
"Cray vectors are only good for numbercrunching and SIMD by
comparison is superior in every way" which is just... blatantly
and demonstrably false even with a basic hand-drawn timing diagram
explained here:

> I really look forward to the new hardware making it to
> market.



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