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Re: instruction cache throttling

Joerg Sommer <joerg@alea.gnuu.de> writes:
> John Steele Scott <toojays@toojays.net> wrote:
>> the ICTC. Try some small odd values like 3 or 7 and see what happens. The
>> information on ICTC usage is from "MPC7450 RISC Microprocessor Family User's
>> Manual", section 10.3.
> I found this document:
> http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/2EF555D341769CE787256E470077DD3D/$file/750gx_um_pub.pdf

Ah, I didn't realise that the IBM chips had ICTC as well. My code checks the
chip type in ict_init. Currently it will only run on the 7450 based CPUs. I
referenced the Motorola datasheet because I have a G4; I had not looked at the
IBM one before.

What CPU are you using?

>> I also started a Wiki page about power consumption on the iBook G4, but
>> currently it has no really new information.
> Where?


I am quite happy for other people to create their own accounts and add more

> In the IBM document I read you need to set HID0[DPM] = 1. I don't know,
> if this is currently done.

It's done in linux/arch/ppc/kernel/cpu_setup_6xx.S, except for the CPUs which
are listed as CPU_FTR_NO_DPM in linux/arch/ppc/kernel/cputable.c. This
includes a couple of 750FX revisions.

> Do you know how to read the ictc register in OSX?

I don't really know anything about OSX. I guess you would need to make some
kind of kernel module, so you can execute code in kernel mode, like you do in



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