[Date Prev][Date Next] [Thread Prev][Thread Next] [Date Index] [Thread Index]

Re: [DRAFT] resolving DFSG violations

On Wed, Oct 29, 2008 at 10:42:56PM +0100, Michelle Konzack wrote:
> Am 2008-10-29 00:39:40, schrieb Ben Hutchings:
> > How exactly do you propose to load the firmware, if not through a JTAG
> > port?  Back in the world of production hardware which Debian runs on,
> > ASICs tend to have power-on-reset logic built-in...
> Most PCI hardware has a very small bootloader which checks some  signals
> on the PCI bus...  I have a book about it but no time to read  in  since
> it is very complicated...

PCI (Express) hardware has to be able to initialise at least the bus
interface and PCI config space at power-on reset.  That includes board-
specific information like subsystem IDs.

The network controllers I work with can initialise their config
registers either from built-in ROM or from external EEPROM or flash,
selected by strap pins.  Production boards always initialise from flash;
thankfully no-one expects to be able to remove flash from NICs as they
need to provide PXE boot code to the host.


Ben Hutchings
It is a miracle that curiosity survives formal education. - Albert Einstein

Attachment: signature.asc
Description: Digital signature

Reply to: