Re: process max virtual memory limit in amd64?

[Karl Magdsick <kmagnum@gmail.com>]

On Fri, 25 Jun 2004 16:30:36 +0300, Alexander Rapp
<alexander@alexander.co.tz> wrote:
> Anders Fugmann wrote:
> > Does anyone know why there is a limitation of 48 bits on the virtual
> > address space, and if it is technically possible to have a 64 bit
> > address space on the AMD64 architecture?
> 
> I was under the impression that memory addressing was limited to 48bits
> on today's amd64s to increase efficiency/performance.  

That would limit physical addressing to 48 bits, not virtual addressing.

> Longer addresses
> take up more space in cache and more bandwidth on the bus.  By
> decreasing the size of every single memory request by 16 bits, more
> instructions can be fit in cache and more can be transmitted in a given
> time.

Reducing the size of the available virtual address space would reduce
the size of the cache line tag, reducing the transistor count for the
logic that checks if a given item is in the cache.  However, the tag
is not counted as part of the capacity of the cache.  I doubt the
amd64 instruction set allows for 48-bit immediate values, so
restricting the virtual address space to 48 bits would not reduce the
amount of space used by instructions in the cache.  However, I do not
have specific knowledge in this matter.  Let me know if you have more
information.

I'm not sure if virtual addressing is limited to 48 bits, but I highly
doubt it would be limited to 48 bits for the reasons given.  More
likely, it would be to reduce transistor count in the MMU and in the
cache logic.


Cheers,
-Karl