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Re: manipulating FPU rounding modes on alpha

On Mon, Sep 10, 2007 at 11:20:21PM +0200, Joachim Reichel wrote:
> this is exactly the same result that I get on Uwe's EV56 without and
> with math_emu. I'm not in the position to discuss whether math_emu
> should be a module or built in.

Using which kernel?

> Your conclusion seems wrong since the test is built with "-mieee
> -mfp-rounding-mode=d -frounding-math".
> Note that the failure is slightly different from that in the build logs on ds10
> (which is an EV6 anyway). Maybe the problem is specific to EV6 and above?

Well I did see some indication that -mieee breaks EV6 and above.  They
were old messages though so who knows what gcc does now.  Why ever did
Digital not just implement ieee floating point properly in the first
place. :)  I am still new to using an alpha, so not quite sure what gcc arguments do what yet.

> Is another alpha developer willing to help? I asked Martin Zobel-Helas
> for an account on ds10, but he is quite busy right now with listmaster
> stuff.
> Lennart, thanks for your help.

No problem.

Certainly the package as it is now builds fine with meth_emu enabled
(loaded as module or built in) on an EV56 (PWD 433au), and the test
fails without math_emu.

Here is my /proc/cpuinfo in case you want to compare against the other
EV56 that supposedly worked fine without math_emu:

cpu                     : Alpha
cpu model               : EV56
cpu variation           : 7
cpu revision            : 0
cpu serial number       :
system type             : Miata
system variation        : 0
system revision         : 0
system serial number    :
cycle frequency [Hz]    : 433149046 est.
timer frequency [Hz]    : 1024.00
page size [bytes]       : 8192
phys. address bits      : 40
max. addr. space #      : 127
BogoMIPS                : 858.04
kernel unaligned acc    : 0 (pc=0,va=0)
user unaligned acc      : 0 (pc=0,va=0)
platform string         : Digital Personal WorkStation 433au
cpus detected           : 1
L1 Icache               : 8K, 1-way, 32b line
L1 Dcache               : 8K, 1-way, 32b line
L2 cache                : 96K, 3-way, 64b line
L3 cache                : 2048K, 1-way, 64b line

Len Sorensen

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