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Hello



Hello

I am trying to write a trap handler to couth the SIGILL and SIGSEVG signals; so if the user program didn't  "mapp" the adr on the vmebus the program will print a message and continue instead of being stop and exit with a core dump.

This is what my program does :
 (a) the "mmap" is done and success , but the physical adr is wrong (e.g. no card on this adr) - error=SIGILL
               (a.1) on "write" to be card I get the msg from my trap handler as many times as I try to write
               (a.2) on "read" - I get my trap handler msg in an endless loop and the program MUST be kill.  I know the trap does not return to the program normal flow (e.g. 1 command after the read) since I have there a printout that it is never reach. 

 (b) if the "mmap" is NOT done at all - error=SIGSEV then I get the endless loop on read or write


           Looking on the vmebus with a data analyzer I can see the bus is being reach every fix period - look like same body is trying to access the memory.

                                 Any idea/help will be great

                                       Thanks in advance

Galia Gitliz
Weizmann Institute of Science
Physics Department, E&DAQ Group
Tel 972-8-9342562
Fax  972-8-9344166
Email : galia.gitliz@weizmann.ac.il
Hello
 
I am trying to write a trap handler to couth the SIGILL and SIGSEVG signals; so if the user program didn't  "mapp" the adr on the vmebus the program will print a message and continue instead of being stop and exit with a core dump.
 
This is what my program does :
 (a) the "mmap" is done and success , but the physical adr is wrong (e.g. no card on this adr) - error=SIGILL
               (a.1) on "write" to be card I get the msg from my trap handler as many times as I try to write
               (a.2) on "read" - I get my trap handler msg in an endless loop and the program MUST be kill.  I know the trap does not return to the program normal flow (e.g. 1 command after the read) since I have there a printout that it is never reach.
 
 (b) if the "mmap" is NOT done at all - error=SIGSEV then I get the endless loop on read or write
 
 
           Looking on the vmebus with a data analyzer I can see the bus is being reach every fix period - look like same body is trying to access the memory.
 
                                 Any idea/help will be great
 
                                       Thanks in advance
 
Galia Gitliz
Weizmann Institute of Science
Physics Department, E&DAQ Group
Tel 972-8-9342562
Fax  972-8-9344166
Email : galia.gitliz@weizmann.ac.il
 
 

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