Andreas Boll pushed to branch debian-unstable at X Strike Force / lib / mesa
Commits:
-
b3eed3ad
by Juan A. Suarez Romero at 2018-04-28T16:57:30+00:00
-
16a3264c
by Juan A. Suarez Romero at 2018-04-30T18:42:38+02:00
-
3e5dfc05
by Jason Ekstrand at 2018-04-30T18:42:38+02:00
-
001f7ac6
by Marek Olšák at 2018-04-30T18:42:39+02:00
-
1fccd673
by Marek Olšák at 2018-04-30T18:42:39+02:00
-
c0aeac15
by Eric Anholt at 2018-04-30T18:42:39+02:00
-
1a23971b
by Leo Liu at 2018-04-30T18:42:39+02:00
-
5a7de464
by Andres Rodriguez at 2018-05-02T12:15:05+02:00
-
97841a8f
by Samuel Pitoiset at 2018-05-02T12:15:05+02:00
-
8f97e569
by Nanley Chery at 2018-05-02T12:15:05+02:00
-
5d3caa1c
by Boyuan Zhang at 2018-05-02T12:15:05+02:00
-
58318369
by Juan A. Suarez Romero at 2018-05-07T10:09:56+00:00
-
6dc2658f
by Juan A. Suarez Romero at 2018-05-07T10:19:36+00:00
-
561494b3
by Andreas Boll at 2018-05-08T09:42:11+02:00
-
5108297d
by Andreas Boll at 2018-05-08T09:43:36+02:00
-
1676bca1
by Andreas Boll at 2018-05-08T10:42:19+02:00
15 changed files:
- VERSION
- bin/.cherry-ignore
- debian/changelog
- docs/relnotes/18.0.2.html
- + docs/relnotes/18.0.3.html
- src/amd/vulkan/radv_pass.c
- src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
- src/gallium/auxiliary/util/u_transfer_helper.c
- src/gallium/drivers/radeon/radeon_vcn_dec.c
- src/gallium/drivers/radeonsi/si_get.c
- src/gallium/state_trackers/omx_bellagio/vid_enc.c
- src/intel/vulkan/anv_allocator.c
- src/mesa/drivers/dri/i965/intel_tex_image.c
- src/util/u_queue.c
- src/util/u_queue.h
Changes:
1 |
-18.0.2
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1 |
+18.0.3
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... | ... | @@ -32,3 +32,10 @@ d136a5fad9c7e67c1362453388914ecc60420883 ac: fix the number of coordinates for a |
32 | 32 |
|
33 | 33 |
# stable: There is a specific port for this patch for stable branch.
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34 | 34 |
fedd0a4215bcd387525000d76b77993ca38916ae radv/winsys: allow to submit up to 4 IBs for chips without chaining
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35 |
+ |
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36 |
+# stable: Explicit 18.1 only nominations
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37 |
+413c5ca3727898fdb4fa1d2849d0c2defdd77b48 travis: update libva required version
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38 |
+a6fbefa67b5b0ed1ee42a9034ee74dfaed1c389a radv: fix DCC enablement since partial MSAA implementation
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39 |
+d7ffe3b384f4d1c15a9364768cf405d416522e60 radv: set ac_surf_info::num_channels correctly
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40 |
+d38425ce872c4a00cfb691ae9dceca6a07afc516 ac: fix texture query LOD for 1D textures on GFX9
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41 |
+4d449c94e450c33d7b2b09c1c263322042503893 autotools, meson: bump up required VA version
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1 |
-mesa (18.0.2-3) UNRELEASED; urgency=medium
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1 |
+mesa (18.0.3-1) unstable; urgency=medium
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2 |
+ |
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3 |
+ [ Andreas Boll ]
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4 |
+ * New upstream release.
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2 | 5 |
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3 | 6 |
[ Nicolas Braud-Santoni ]
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4 | 7 |
* Add debian/gbp.conf.
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... | ... | @@ -7,7 +10,7 @@ mesa (18.0.2-3) UNRELEASED; urgency=medium |
7 | 10 |
* control: libegl1-mesa-dev should pull the new libwayland-dev, update
|
8 | 11 |
dependency.
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9 | 12 |
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10 |
- -- Andreas Boll <aboll@debian.org> Wed, 02 May 2018 19:42:26 +0200
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13 |
+ -- Andreas Boll <aboll@debian.org> Tue, 08 May 2018 10:42:07 +0200
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11 | 14 |
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12 | 15 |
mesa (18.0.2-2) unstable; urgency=medium
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13 | 16 |
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... | ... | @@ -31,7 +31,8 @@ because compatibility contexts are not supported. |
31 | 31 |
|
32 | 32 |
<h2>SHA256 checksums</h2>
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33 | 33 |
<pre>
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34 |
-TBD
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34 |
+SHA256: ffd8dfe3337b474a3baa085f0e7ef1a32c7cdc3bed1ad810b2633919a9324840 mesa-18.0.2.tar.gz
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35 |
+SHA256: 98fa159768482dc568b9f8bf0f36c7acb823fa47428ffd650b40784f16b9e7b3 mesa-18.0.2.tar.xz
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35 | 36 |
</pre>
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36 | 37 |
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37 | 38 |
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1 |
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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2 |
+<html lang="en">
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3 |
+<head>
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4 |
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
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5 |
+ <title>Mesa Release Notes</title>
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6 |
+ <link rel="stylesheet" type="text/css" href="">"../mesa.css">
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7 |
+</head>
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8 |
+<body>
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9 |
+ |
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10 |
+<div class="header">
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11 |
+ <h1>The Mesa 3D Graphics Library</h1>
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12 |
+</div>
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13 |
+ |
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14 |
+<iframe src="">"../contents.html"></iframe>
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15 |
+<div class="content">
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16 |
+ |
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17 |
+<h1>Mesa 18.0.3 Release Notes / May 7, 2018</h1>
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18 |
+ |
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19 |
+<p>
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20 |
+Mesa 18.0.3 is a bug fix release which fixes bugs found since the 18.0.2 release.
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21 |
+</p>
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22 |
+<p>
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23 |
+Mesa 18.0.3 implements the OpenGL 4.5 API, but the version reported by
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24 |
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
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25 |
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
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26 |
+Some drivers don't support all the features required in OpenGL 4.5. OpenGL
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27 |
+4.5 is <strong>only</strong> available if requested at context creation
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28 |
+because compatibility contexts are not supported.
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29 |
+</p>
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30 |
+ |
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31 |
+ |
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32 |
+<h2>SHA256 checksums</h2>
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33 |
+<pre>
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34 |
+TBD
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35 |
+</pre>
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36 |
+ |
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37 |
+ |
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38 |
+<h2>New features</h2>
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39 |
+<p>None</p>
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40 |
+ |
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41 |
+ |
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42 |
+<h2>Bug fixes</h2>
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43 |
+ |
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44 |
+<ul>
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45 |
+ |
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46 |
+<li><a href="">"https://bugs.freedesktop.org/show_bug.cgi?id=105374">Bug 105374</a> - texture3d, a SaschaWillems demo, assert fails</li>
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47 |
+ |
|
48 |
+<li><a href="">"https://bugs.freedesktop.org/show_bug.cgi?id=106147">Bug 106147</a> - SIGBUS in write_reloc() when Sacha Willems' "texture3d" Vulkan demo starts</li>
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49 |
+ |
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50 |
+</ul>
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51 |
+ |
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52 |
+ |
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53 |
+<h2>Changes</h2>
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54 |
+ |
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55 |
+<p>Andres Rodriguez (1):</p>
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56 |
+<ul>
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57 |
+ <li>radv/winsys: fix leaking resources from bo's imported by fd</li>
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58 |
+</ul>
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59 |
+ |
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60 |
+<p>Boyuan Zhang (1):</p>
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61 |
+<ul>
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62 |
+ <li>radeon/vcn: fix mpeg4 msg buffer settings</li>
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63 |
+</ul>
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64 |
+ |
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65 |
+<p>Eric Anholt (1):</p>
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66 |
+<ul>
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67 |
+ <li>gallium/util: Fix incorrect refcounting of separate stencil.</li>
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68 |
+</ul>
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69 |
+ |
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70 |
+<p>Jason Ekstrand (1):</p>
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71 |
+<ul>
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72 |
+ <li>anv/allocator: Don't shrink either end of the block pool</li>
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73 |
+</ul>
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74 |
+ |
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75 |
+<p>Juan A. Suarez Romero (3):</p>
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76 |
+<ul>
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77 |
+ <li>docs: add sha256 checksums for 18.0.2</li>
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78 |
+ <li>cherry-ignore: add explicit 18.1 only nominations</li>
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79 |
+ <li>Update version to 18.0.3</li>
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80 |
+</ul>
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81 |
+ |
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82 |
+<p>Leo Liu (1):</p>
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83 |
+<ul>
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84 |
+ <li>st/omx/enc: fix blit setup for YUV LoadImage</li>
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85 |
+</ul>
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86 |
+ |
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87 |
+<p>Marek Olšák (2):</p>
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88 |
+<ul>
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89 |
+ <li>util/u_queue: fix a deadlock in util_queue_finish</li>
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90 |
+ <li>radeonsi/gfx9: workaround for INTERP with indirect indexing</li>
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91 |
+</ul>
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92 |
+ |
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93 |
+<p>Nanley Chery (1):</p>
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94 |
+<ul>
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95 |
+ <li>i965/tex_image: Avoid the ASTC LDR workaround on gen9lp</li>
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96 |
+</ul>
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97 |
+ |
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98 |
+<p>Samuel Pitoiset (1):</p>
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99 |
+<ul>
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100 |
+ <li>radv: compute the number of subpass attachments correctly</li>
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101 |
+</ul>
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102 |
+ |
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103 |
+ |
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104 |
+</div>
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105 |
+</body>
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106 |
+</html>
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... | ... | @@ -87,8 +87,8 @@ VkResult radv_CreateRenderPass( |
87 | 87 |
subpass_attachment_count +=
|
88 | 88 |
desc->inputAttachmentCount +
|
89 | 89 |
desc->colorAttachmentCount +
|
90 |
- /* Count colorAttachmentCount again for resolve_attachments */
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91 |
- desc->colorAttachmentCount;
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90 |
+ (desc->pResolveAttachments ? desc->colorAttachmentCount : 0) +
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91 |
+ (desc->pDepthStencilAttachment != NULL);
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|
92 | 92 |
}
|
93 | 93 |
|
94 | 94 |
if (subpass_attachment_count) {
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... | ... | @@ -450,6 +450,7 @@ radv_amdgpu_winsys_bo_from_fd(struct radeon_winsys *_ws, |
450 | 450 |
bo->size = result.alloc_size;
|
451 | 451 |
bo->is_shared = true;
|
452 | 452 |
bo->ws = ws;
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453 |
+ bo->ref_count = 1;
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|
453 | 454 |
radv_amdgpu_add_buffer_to_global_list(bo);
|
454 | 455 |
return (struct radeon_winsys_bo *)bo;
|
455 | 456 |
error_va_map:
|
... | ... | @@ -138,8 +138,7 @@ u_transfer_helper_resource_destroy(struct pipe_screen *pscreen, |
138 | 138 |
if (helper->vtbl->get_stencil) {
|
139 | 139 |
struct pipe_resource *stencil = helper->vtbl->get_stencil(prsc);
|
140 | 140 |
|
141 |
- if (stencil)
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142 |
- helper->vtbl->resource_destroy(pscreen, stencil);
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|
141 |
+ pipe_resource_reference(&stencil, NULL);
|
|
143 | 142 |
}
|
144 | 143 |
|
145 | 144 |
helper->vtbl->resource_destroy(pscreen, prsc);
|
... | ... | @@ -554,15 +554,15 @@ static rvcn_dec_message_mpeg4_asp_vld_t get_mpeg4_msg(struct radeon_decoder *dec |
554 | 554 |
|
555 | 555 |
result.vop_time_increment_resolution = pic->vop_time_increment_resolution;
|
556 | 556 |
|
557 |
- result.short_video_header |= pic->short_video_header << 0;
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558 |
- result.interlaced |= pic->interlaced << 2;
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559 |
- result.load_intra_quant_mat |= 1 << 3;
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|
560 |
- result.load_nonintra_quant_mat |= 1 << 4;
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561 |
- result.quarter_sample |= pic->quarter_sample << 5;
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562 |
- result.complexity_estimation_disable |= 1 << 6;
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563 |
- result.resync_marker_disable |= pic->resync_marker_disable << 7;
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564 |
- result.newpred_enable |= 0 << 10; //
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565 |
- result.reduced_resolution_vop_enable |= 0 << 11;
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|
557 |
+ result.short_video_header = pic->short_video_header;
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558 |
+ result.interlaced = pic->interlaced;
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559 |
+ result.load_intra_quant_mat = 1;
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|
560 |
+ result.load_nonintra_quant_mat = 1;
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561 |
+ result.quarter_sample = pic->quarter_sample;
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562 |
+ result.complexity_estimation_disable = 1;
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563 |
+ result.resync_marker_disable = pic->resync_marker_disable;
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|
564 |
+ result.newpred_enable = 0;
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565 |
+ result.reduced_resolution_vop_enable = 0;
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|
566 | 566 |
|
567 | 567 |
result.quant_type = pic->quant_type;
|
568 | 568 |
|
... | ... | @@ -470,12 +470,19 @@ static int si_get_shader_param(struct pipe_screen* pscreen, |
470 | 470 |
|
471 | 471 |
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
|
472 | 472 |
/* TODO: Indirect indexing of GS inputs is unimplemented. */
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473 |
- return shader != PIPE_SHADER_GEOMETRY &&
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|
474 |
- (sscreen->llvm_has_working_vgpr_indexing ||
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475 |
- /* TCS and TES load inputs directly from LDS or
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476 |
- * offchip memory, so indirect indexing is trivial. */
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|
477 |
- shader == PIPE_SHADER_TESS_CTRL ||
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478 |
- shader == PIPE_SHADER_TESS_EVAL);
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473 |
+ if (shader == PIPE_SHADER_GEOMETRY)
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474 |
+ return 0;
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475 |
+ |
|
476 |
+ if (shader == PIPE_SHADER_VERTEX &&
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477 |
+ !sscreen->llvm_has_working_vgpr_indexing)
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478 |
+ return 0;
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479 |
+ |
|
480 |
+ /* TCS and TES load inputs directly from LDS or offchip
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|
481 |
+ * memory, so indirect indexing is always supported.
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482 |
+ * PS has to support indirect indexing, because we can't
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|
483 |
+ * lower that to TEMPs for INTERP instructions.
|
|
484 |
+ */
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|
485 |
+ return 1;
|
|
479 | 486 |
|
480 | 487 |
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
|
481 | 488 |
return sscreen->llvm_has_working_vgpr_indexing ||
|
... | ... | @@ -934,7 +934,7 @@ static OMX_ERRORTYPE enc_LoadImage(omx_base_PortType *port, OMX_BUFFERHEADERTYPE |
934 | 934 |
blit.src.resource = inp->resource;
|
935 | 935 |
blit.src.format = inp->resource->format;
|
936 | 936 |
|
937 |
- blit.src.box.x = 0;
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|
937 |
+ blit.src.box.x = -1;
|
|
938 | 938 |
blit.src.box.y = def->nFrameHeight;
|
939 | 939 |
blit.src.box.width = def->nFrameWidth;
|
940 | 940 |
blit.src.box.height = def->nFrameHeight / 2 ;
|
... | ... | @@ -948,11 +948,11 @@ static OMX_ERRORTYPE enc_LoadImage(omx_base_PortType *port, OMX_BUFFERHEADERTYPE |
948 | 948 |
blit.dst.box.depth = 1;
|
949 | 949 |
blit.filter = PIPE_TEX_FILTER_NEAREST;
|
950 | 950 |
|
951 |
- blit.mask = PIPE_MASK_G;
|
|
951 |
+ blit.mask = PIPE_MASK_R;
|
|
952 | 952 |
priv->s_pipe->blit(priv->s_pipe, &blit);
|
953 | 953 |
|
954 |
- blit.src.box.x = 1;
|
|
955 |
- blit.mask = PIPE_MASK_R;
|
|
954 |
+ blit.src.box.x = 0;
|
|
955 |
+ blit.mask = PIPE_MASK_G;
|
|
956 | 956 |
priv->s_pipe->blit(priv->s_pipe, &blit);
|
957 | 957 |
priv->s_pipe->flush(priv->s_pipe, NULL, 0);
|
958 | 958 |
|
... | ... | @@ -508,12 +508,12 @@ anv_block_pool_grow(struct anv_block_pool *pool, struct anv_block_state *state) |
508 | 508 |
assert(center_bo_offset >= back_used);
|
509 | 509 |
|
510 | 510 |
/* Make sure we don't shrink the back end of the pool */
|
511 |
- if (center_bo_offset < pool->back_state.end)
|
|
512 |
- center_bo_offset = pool->back_state.end;
|
|
511 |
+ if (center_bo_offset < back_required)
|
|
512 |
+ center_bo_offset = back_required;
|
|
513 | 513 |
|
514 | 514 |
/* Make sure that we don't shrink the front end of the pool */
|
515 |
- if (size - center_bo_offset < pool->state.end)
|
|
516 |
- center_bo_offset = size - pool->state.end;
|
|
515 |
+ if (size - center_bo_offset < front_required)
|
|
516 |
+ center_bo_offset = size - front_required;
|
|
517 | 517 |
}
|
518 | 518 |
|
519 | 519 |
assert(center_bo_offset % PAGE_SIZE == 0);
|
... | ... | @@ -871,7 +871,7 @@ intelCompressedTexSubImage(struct gl_context *ctx, GLuint dims, |
871 | 871 |
!_mesa_is_srgb_format(gl_format);
|
872 | 872 |
struct brw_context *brw = (struct brw_context*) ctx;
|
873 | 873 |
const struct gen_device_info *devinfo = &brw->screen->devinfo;
|
874 |
- if (devinfo->gen == 9 && is_linear_astc)
|
|
874 |
+ if (devinfo->gen == 9 && !gen_device_info_is_9lp(devinfo) && is_linear_astc)
|
|
875 | 875 |
flush_astc_denorms(ctx, dims, texImage,
|
876 | 876 |
xoffset, yoffset, zoffset,
|
877 | 877 |
width, height, depth);
|
... | ... | @@ -311,6 +311,7 @@ util_queue_init(struct util_queue *queue, |
311 | 311 |
goto fail;
|
312 | 312 |
|
313 | 313 |
(void) mtx_init(&queue->lock, mtx_plain);
|
314 |
+ (void) mtx_init(&queue->finish_lock, mtx_plain);
|
|
314 | 315 |
|
315 | 316 |
queue->num_queued = 0;
|
316 | 317 |
cnd_init(&queue->has_queued_cond);
|
... | ... | @@ -398,6 +399,7 @@ util_queue_destroy(struct util_queue *queue) |
398 | 399 |
|
399 | 400 |
cnd_destroy(&queue->has_space_cond);
|
400 | 401 |
cnd_destroy(&queue->has_queued_cond);
|
402 |
+ mtx_destroy(&queue->finish_lock);
|
|
401 | 403 |
mtx_destroy(&queue->lock);
|
402 | 404 |
free(queue->jobs);
|
403 | 405 |
free(queue->threads);
|
... | ... | @@ -529,6 +531,12 @@ util_queue_finish(struct util_queue *queue) |
529 | 531 |
|
530 | 532 |
util_barrier_init(&barrier, queue->num_threads);
|
531 | 533 |
|
534 |
+ /* If 2 threads were adding jobs for 2 different barries at the same time,
|
|
535 |
+ * a deadlock would happen, because 1 barrier requires that all threads
|
|
536 |
+ * wait for it exclusively.
|
|
537 |
+ */
|
|
538 |
+ mtx_lock(&queue->finish_lock);
|
|
539 |
+ |
|
532 | 540 |
for (unsigned i = 0; i < queue->num_threads; ++i) {
|
533 | 541 |
util_queue_fence_init(&fences[i]);
|
534 | 542 |
util_queue_add_job(queue, &barrier, &fences[i], util_queue_finish_execute, NULL);
|
... | ... | @@ -538,6 +546,7 @@ util_queue_finish(struct util_queue *queue) |
538 | 546 |
util_queue_fence_wait(&fences[i]);
|
539 | 547 |
util_queue_fence_destroy(&fences[i]);
|
540 | 548 |
}
|
549 |
+ mtx_unlock(&queue->finish_lock);
|
|
541 | 550 |
|
542 | 551 |
util_barrier_destroy(&barrier);
|
543 | 552 |
|
... | ... | @@ -200,6 +200,7 @@ struct util_queue_job { |
200 | 200 |
/* Put this into your context. */
|
201 | 201 |
struct util_queue {
|
202 | 202 |
const char *name;
|
203 |
+ mtx_t finish_lock; /* only for util_queue_finish */
|
|
203 | 204 |
mtx_t lock;
|
204 | 205 |
cnd_t has_queued_cond;
|
205 | 206 |
cnd_t has_space_cond;
|