[Git][xorg-team/lib/mesa][upstream-unstable] 13 commits: docs: add sha256 checksums for 18.0.2

Andreas Boll pushed to branch upstream-unstable at X Strike Force / lib / mesa

Commits:

b3eed3ad

by Juan A. Suarez Romero at 2018-04-28T16:57:30+00:00

docs: add sha256 checksums for 18.0.2

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

16a3264c

by Juan A. Suarez Romero at 2018-04-30T18:42:38+02:00

cherry-ignore: add explicit 18.1 only nominations

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

3e5dfc05

by Jason Ekstrand at 2018-04-30T18:42:38+02:00

anv/allocator: Don't shrink either end of the block pool

Previously, we only tried to ensure that we didn't shrink either end
below what was already handed out.  However, due to the way we handle
relocations with block pools, we can't shrink the back end at all.  It's
probably best to not shrink in either direction.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105374
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106147
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 3db93f9128e5329f6658c9018cf23eb31807c24c)

001f7ac6

by Marek Olšák at 2018-04-30T18:42:39+02:00

util/u_queue: fix a deadlock in util_queue_finish

Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 7083ac7290a0c37a45494437a45441112f3cc36c)

1fccd673

by Marek Olšák at 2018-04-30T18:42:39+02:00

radeonsi/gfx9: workaround for INTERP with indirect indexing

and clean up the conditions.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 6d19120da851c0d3f97376c733d674f7c8ab0457)

c0aeac15

by Eric Anholt at 2018-04-30T18:42:39+02:00

gallium/util: Fix incorrect refcounting of separate stencil.

The driver may have a reference on the separate stencil buffer for some
reason (like an unflushed job using it), so we can't directly free the
resource and should instead just decrement the refcount that we own.
Fixes double-free in KHR-GLES3.packed_depth_stencil.blit.depth32f_stencil8
on vc5.

Fixes: e94eb5e6000e ("gallium/util: add u_transfer_helper")
Reviewed-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit 069c409f434ab215940aad2092d5d236b410a7b9)

1a23971b

by Leo Liu at 2018-04-30T18:42:39+02:00

st/omx/enc: fix blit setup for YUV LoadImage

The blit here involves scaling since it's copying from I8 format to R8G8 format.
Half of source will be filtered out with PIPE_TEX_FILTER_NEAREST instruction, it
looks that GPU always uses the second half as source. Currently we use "1" as
the start point of x for R, then causing 1 source pixel of U component shift to
right. So "-1" should be the start point for U component.

Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 1c5f4f4e17f74d823d9e38c678e40e9f49e2c053)
[Juan A. Suarez: apply patch in
src/gallium/state_trackers/omx_bellagio/vid_enc.c]
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

Conflicts:
	src/gallium/state_trackers/omx/vid_enc_common.c

5a7de464

by Andres Rodriguez at 2018-05-02T12:15:05+02:00

radv/winsys: fix leaking resources from bo's imported by fd

A bo's ref_count was not being initialized when imported from an fd.
Therefore, we would fail to free the resource during VkFreeMemory().

This patch fixes applications like hifi VR in threaded mode, which
perform frequent imports/releases of IPC shared memory.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit f56e22e49673e8234a7fe0c241b4c3eae4752f34)

97841a8f

by Samuel Pitoiset at 2018-05-02T12:15:05+02:00

radv: compute the number of subpass attachments correctly

Only count color attachments twice if resolves are used, also
account for the depth stencil attachment if present.

Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit d8db5986cee83078e46895d695d698db87507019)

8f97e569

by Nanley Chery at 2018-05-02T12:15:05+02:00

i965/tex_image: Avoid the ASTC LDR workaround on gen9lp

Both the internal documentation and the results of testing this in the
CI suggest that this is unnecessary. Add the fixes tag because this
reduces an internal benchmark's startup time by about 17 seconds
(reported by Eero).

Fixes: 710b1d2e665 "i965/tex_image: Flush certain subnormal ASTC channel values"
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 3e56e4642fb5875b3f5c4eb34798ba9f3d827705)

5d3caa1c

by Boyuan Zhang at 2018-05-02T12:15:05+02:00

radeon/vcn: fix mpeg4 msg buffer settings

Previous bit-fields assignments are incorrect and will result certain mpeg4
decode failed due to wrong flag values. This patch fixes these assignments.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
(cherry picked from commit deba56accf4e1f8fc025f34f6cbc069285f76838)

58318369

by Juan A. Suarez Romero at 2018-05-07T10:09:56+00:00

Update version to 18.0.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

6dc2658f

by Juan A. Suarez Romero at 2018-05-07T10:19:36+00:00

docs: add sha256 checksums for 18.0.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

14 changed files:

VERSION
bin/.cherry-ignore
docs/relnotes/18.0.2.html
+ docs/relnotes/18.0.3.html
src/amd/vulkan/radv_pass.c
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
src/gallium/auxiliary/util/u_transfer_helper.c
src/gallium/drivers/radeon/radeon_vcn_dec.c
src/gallium/drivers/radeonsi/si_get.c
src/gallium/state_trackers/omx_bellagio/vid_enc.c
src/intel/vulkan/anv_allocator.c
src/mesa/drivers/dri/i965/intel_tex_image.c
src/util/u_queue.c
src/util/u_queue.h

Changes:

VERSION

1		-18.0.2
	1	+18.0.3

bin/.cherry-ignore

@@ -32,3 +32,10 @@ d136a5fad9c7e67c1362453388914ecc60420883 ac: fix the number of coordinates for a
  # stable: There is a specific port for this patch for stable branch.
  fedd0a4215bcd387525000d76b77993ca38916ae radv/winsys: allow to submit up to 4 IBs for chips without chaining
++
 +# stable: Explicit 18.1 only nominations
 +413c5ca3727898fdb4fa1d2849d0c2defdd77b48 travis: update libva required version
 +a6fbefa67b5b0ed1ee42a9034ee74dfaed1c389a radv: fix DCC enablement since partial MSAA implementation
 +d7ffe3b384f4d1c15a9364768cf405d416522e60 radv: set ac_surf_info::num_channels correctly
 +d38425ce872c4a00cfb691ae9dceca6a07afc516 ac: fix texture query LOD for 1D textures on GFX9
 +4d449c94e450c33d7b2b09c1c263322042503893 autotools, meson: bump up required VA version

docs/relnotes/18.0.2.html

@@ -31,7 +31,8 @@ because compatibility contexts are not supported.
  <h2>SHA256 checksums</h2>
  <pre>
 -TBD
 +SHA256: ffd8dfe3337b474a3baa085f0e7ef1a32c7cdc3bed1ad810b2633919a9324840  mesa-18.0.2.tar.gz
 +SHA256: 98fa159768482dc568b9f8bf0f36c7acb823fa47428ffd650b40784f16b9e7b3  mesa-18.0.2.tar.xz
  </pre>

docs/relnotes/18.0.3.html

 +<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
 +<html lang="en">
 +<head>
 +  <meta http-equiv="content-type" content="text/html; charset=utf-8">
 +  <title>Mesa Release Notes</title>
 +  <link rel="stylesheet" type="text/css" href="">"../mesa.css">
 +</head>
 +<body>
++
 +<div class="header">
 +  <h1>The Mesa 3D Graphics Library</h1>
 +</div>
++
 +<iframe src="">"../contents.html"></iframe>
 +<div class="content">
++
 +<h1>Mesa 18.0.3 Release Notes / May 7, 2018</h1>
++
 +<p>
 +Mesa 18.0.3 is a bug fix release which fixes bugs found since the 18.0.2 release.
 +</p>
 +<p>
 +Mesa 18.0.3 implements the OpenGL 4.5 API, but the version reported by
 +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
 +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
 +Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
 +4.5 is <strong>only</strong> available if requested at context creation
 +because compatibility contexts are not supported.
 +</p>
++
++
 +<h2>SHA256 checksums</h2>
 +<pre>
 +TBD
 +</pre>
++
++
 +<h2>New features</h2>
 +<p>None</p>
++
++
 +<h2>Bug fixes</h2>
++
 +<ul>
++
 +<li><a href="">"https://bugs.freedesktop.org/show_bug.cgi?id=105374">Bug 105374</a> - texture3d, a SaschaWillems demo, assert fails</li>
++
 +<li><a href="">"https://bugs.freedesktop.org/show_bug.cgi?id=106147">Bug 106147</a> - SIGBUS in write_reloc() when Sacha Willems' &quot;texture3d&quot; Vulkan demo starts</li>
++
 +</ul>
++
++
 +<h2>Changes</h2>
++
 +<p>Andres Rodriguez (1):</p>
 +<ul>
 +  <li>radv/winsys: fix leaking resources from bo's imported by fd</li>
 +</ul>
++
 +<p>Boyuan Zhang (1):</p>
 +<ul>
 +  <li>radeon/vcn: fix mpeg4 msg buffer settings</li>
 +</ul>
++
 +<p>Eric Anholt (1):</p>
 +<ul>
 +  <li>gallium/util: Fix incorrect refcounting of separate stencil.</li>
 +</ul>
++
 +<p>Jason Ekstrand (1):</p>
 +<ul>
 +  <li>anv/allocator: Don't shrink either end of the block pool</li>
 +</ul>
++
 +<p>Juan A. Suarez Romero (3):</p>
 +<ul>
 +  <li>docs: add sha256 checksums for 18.0.2</li>
 +  <li>cherry-ignore: add explicit 18.1 only nominations</li>
 +  <li>Update version to 18.0.3</li>
 +</ul>
++
 +<p>Leo Liu (1):</p>
 +<ul>
 +  <li>st/omx/enc: fix blit setup for YUV LoadImage</li>
 +</ul>
++
 +<p>Marek Olšák (2):</p>
 +<ul>
 +  <li>util/u_queue: fix a deadlock in util_queue_finish</li>
 +  <li>radeonsi/gfx9: workaround for INTERP with indirect indexing</li>
 +</ul>
++
 +<p>Nanley Chery (1):</p>
 +<ul>
 +  <li>i965/tex_image: Avoid the ASTC LDR workaround on gen9lp</li>
 +</ul>
++
 +<p>Samuel Pitoiset (1):</p>
 +<ul>
 +  <li>radv: compute the number of subpass attachments correctly</li>
 +</ul>
++
++
 +</div>
 +</body>
 +</html>

src/amd/vulkan/radv_pass.c

@@ -87,8 +87,8 @@ VkResult radv_CreateRenderPass(
  		subpass_attachment_count +=
  			desc->inputAttachmentCount +
  			desc->colorAttachmentCount +
 -			/* Count colorAttachmentCount again for resolve_attachments */
 -			desc->colorAttachmentCount;
 +			(desc->pResolveAttachments ? desc->colorAttachmentCount : 0) +
 +			(desc->pDepthStencilAttachment != NULL);
+ 	}
  	if (subpass_attachment_count) {

src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c

@@ -450,6 +450,7 @@ radv_amdgpu_winsys_bo_from_fd(struct radeon_winsys *_ws,
  	bo->size = result.alloc_size;
  	bo->is_shared = true;
  	bo->ws = ws;
 +	bo->ref_count = 1;
  	radv_amdgpu_add_buffer_to_global_list(bo);
  	return (struct radeon_winsys_bo *)bo;
  error_va_map:

src/gallium/auxiliary/util/u_transfer_helper.c

@@ -138,8 +138,7 @@ u_transfer_helper_resource_destroy(struct pipe_screen *pscreen,
     if (helper->vtbl->get_stencil) {
        struct pipe_resource *stencil = helper->vtbl->get_stencil(prsc);
 -      if (stencil)
 -         helper->vtbl->resource_destroy(pscreen, stencil);
 +      pipe_resource_reference(&stencil, NULL);
+    }
     helper->vtbl->resource_destroy(pscreen, prsc);

src/gallium/drivers/radeon/radeon_vcn_dec.c

@@ -554,15 +554,15 @@ static rvcn_dec_message_mpeg4_asp_vld_t get_mpeg4_msg(struct radeon_decoder *dec
  	result.vop_time_increment_resolution = pic->vop_time_increment_resolution;
 -	result.short_video_header |= pic->short_video_header << 0;
 -	result.interlaced |= pic->interlaced << 2;
 -        result.load_intra_quant_mat |= 1 << 3;
 -	result.load_nonintra_quant_mat |= 1 << 4;
 -	result.quarter_sample |= pic->quarter_sample << 5;
 -	result.complexity_estimation_disable |= 1 << 6;
 -	result.resync_marker_disable |= pic->resync_marker_disable << 7;
 -	result.newpred_enable |= 0 << 10; //
 -	result.reduced_resolution_vop_enable |= 0 << 11;
 +	result.short_video_header = pic->short_video_header;
 +	result.interlaced = pic->interlaced;
 +	result.load_intra_quant_mat = 1;
 +	result.load_nonintra_quant_mat = 1;
 +	result.quarter_sample = pic->quarter_sample;
 +	result.complexity_estimation_disable = 1;
 +	result.resync_marker_disable = pic->resync_marker_disable;
 +	result.newpred_enable = 0;
 +	result.reduced_resolution_vop_enable = 0;
  	result.quant_type = pic->quant_type;

src/gallium/drivers/radeonsi/si_get.c

@@ -470,12 +470,19 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
  	case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
  		/* TODO: Indirect indexing of GS inputs is unimplemented. */
 -		return shader != PIPE_SHADER_GEOMETRY &&
 -		       (sscreen->llvm_has_working_vgpr_indexing ||
 -			/* TCS and TES load inputs directly from LDS or
 -			 * offchip memory, so indirect indexing is trivial. */
 -			shader == PIPE_SHADER_TESS_CTRL ||
 -			shader == PIPE_SHADER_TESS_EVAL);
 +		if (shader == PIPE_SHADER_GEOMETRY)
 +			return 0;
++
 +		if (shader == PIPE_SHADER_VERTEX &&
 +		    !sscreen->llvm_has_working_vgpr_indexing)
 +			return 0;
++
 +		/* TCS and TES load inputs directly from LDS or offchip
 +		 * memory, so indirect indexing is always supported.
 +		 * PS has to support indirect indexing, because we can't
 +		 * lower that to TEMPs for INTERP instructions.
 +		 */
 +		return 1;
  	case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
  		return sscreen->llvm_has_working_vgpr_indexing ||

src/gallium/state_trackers/omx_bellagio/vid_enc.c

@@ -934,7 +934,7 @@ static OMX_ERRORTYPE enc_LoadImage(omx_base_PortType *port, OMX_BUFFERHEADERTYPE
        blit.src.resource = inp->resource;
        blit.src.format = inp->resource->format;
 -      blit.src.box.x = 0;
 +      blit.src.box.x = -1;
        blit.src.box.y = def->nFrameHeight;
        blit.src.box.width = def->nFrameWidth;
        blit.src.box.height = def->nFrameHeight / 2 ;
@@ -948,11 +948,11 @@ static OMX_ERRORTYPE enc_LoadImage(omx_base_PortType *port, OMX_BUFFERHEADERTYPE
        blit.dst.box.depth = 1;
        blit.filter = PIPE_TEX_FILTER_NEAREST;
 -      blit.mask = PIPE_MASK_G;
 +      blit.mask = PIPE_MASK_R;
        priv->s_pipe->blit(priv->s_pipe, &blit);
 -      blit.src.box.x = 1;
 -      blit.mask = PIPE_MASK_R;
 +      blit.src.box.x = 0;
 +      blit.mask = PIPE_MASK_G;
        priv->s_pipe->blit(priv->s_pipe, &blit);
        priv->s_pipe->flush(priv->s_pipe, NULL, 0);

src/intel/vulkan/anv_allocator.c

@@ -508,12 +508,12 @@ anv_block_pool_grow(struct anv_block_pool *pool, struct anv_block_state *state)
        assert(center_bo_offset >= back_used);
        /* Make sure we don't shrink the back end of the pool */
 -      if (center_bo_offset < pool->back_state.end)
 -         center_bo_offset = pool->back_state.end;
 +      if (center_bo_offset < back_required)
 +         center_bo_offset = back_required;
        /* Make sure that we don't shrink the front end of the pool */
 -      if (size - center_bo_offset < pool->state.end)
 -         center_bo_offset = size - pool->state.end;
 +      if (size - center_bo_offset < front_required)
 +         center_bo_offset = size - front_required;
+    }
     assert(center_bo_offset % PAGE_SIZE == 0);

src/mesa/drivers/dri/i965/intel_tex_image.c

@@ -871,7 +871,7 @@ intelCompressedTexSubImage(struct gl_context *ctx, GLuint dims,
                          !_mesa_is_srgb_format(gl_format);
     struct brw_context *brw = (struct brw_context*) ctx;
     const struct gen_device_info *devinfo = &brw->screen->devinfo;
 -   if (devinfo->gen == 9 && is_linear_astc)
 +   if (devinfo->gen == 9 && !gen_device_info_is_9lp(devinfo) && is_linear_astc)
        flush_astc_denorms(ctx, dims, texImage,
                           xoffset, yoffset, zoffset,
                           width, height, depth);

src/util/u_queue.c

@@ -311,6 +311,7 @@ util_queue_init(struct util_queue *queue,
        goto fail;
     (void) mtx_init(&queue->lock, mtx_plain);
 +   (void) mtx_init(&queue->finish_lock, mtx_plain);
     queue->num_queued = 0;
     cnd_init(&queue->has_queued_cond);
@@ -398,6 +399,7 @@ util_queue_destroy(struct util_queue *queue)
     cnd_destroy(&queue->has_space_cond);
     cnd_destroy(&queue->has_queued_cond);
 +   mtx_destroy(&queue->finish_lock);
     mtx_destroy(&queue->lock);
     free(queue->jobs);
     free(queue->threads);
@@ -529,6 +531,12 @@ util_queue_finish(struct util_queue *queue)
     util_barrier_init(&barrier, queue->num_threads);
 +   /* If 2 threads were adding jobs for 2 different barries at the same time,
 +    * a deadlock would happen, because 1 barrier requires that all threads
 +    * wait for it exclusively.
 +    */
 +   mtx_lock(&queue->finish_lock);
++
     for (unsigned i = 0; i < queue->num_threads; ++i) {
        util_queue_fence_init(&fences[i]);
        util_queue_add_job(queue, &barrier, &fences[i], util_queue_finish_execute, NULL);
@@ -538,6 +546,7 @@ util_queue_finish(struct util_queue *queue)
        util_queue_fence_wait(&fences[i]);
        util_queue_fence_destroy(&fences[i]);
+    }
 +   mtx_unlock(&queue->finish_lock);
     util_barrier_destroy(&barrier);

src/util/u_queue.h

@@ -200,6 +200,7 @@ struct util_queue_job {
  /* Put this into your context. */
  struct util_queue {
     const char *name;
 +   mtx_t finish_lock; /* only for util_queue_finish */
     mtx_t lock;
     cnd_t has_queued_cond;
     cnd_t has_space_cond;