mesa: Changes to 'upstream-unstable'
.travis.yml | 32 -
VERSION | 2
bin/.cherry-ignore | 5
docs/llvmpipe.html | 12
docs/relnotes/17.3.0.html | 3
docs/relnotes/17.3.1.html | 190 ++++++++++
src/amd/vulkan/radv_device.c | 61 +--
src/amd/vulkan/radv_extensions.py | 1
src/amd/vulkan/radv_meta_blit.c | 49 +-
src/amd/vulkan/radv_pipeline.c | 40 ++
src/amd/vulkan/radv_private.h | 2
src/compiler/glsl/builtin_variables.cpp | 4
src/compiler/glsl/link_varyings.cpp | 6
src/compiler/nir/nir.h | 6
src/compiler/nir/nir_metadata.c | 2
src/compiler/nir/nir_opcodes.py | 4
src/compiler/nir/nir_validate.c | 2
src/compiler/spirv/vtn_variables.c | 58 +--
src/gallium/auxiliary/util/u_resource.c | 3
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 2
src/gallium/drivers/r600/sb/sb_if_conversion.cpp | 2
src/gallium/drivers/r600/sb/sb_ir.cpp | 2
src/gallium/drivers/r600/sb/sb_ir.h | 3
src/gallium/drivers/radeon/r600_buffer_common.c | 2
src/gallium/drivers/radeon/r600_texture.c | 19 -
src/gallium/drivers/radeon/radeon_vce.c | 2
src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c | 2
src/gallium/drivers/swr/rasterizer/core/threads.cpp | 3
src/gallium/drivers/vc4/vc4_draw.c | 43 +-
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 5
src/glx/dri3_glx.c | 5
src/mesa/drivers/common/meta.c | 30 -
src/mesa/drivers/dri/i965/brw_blorp.c | 17
src/mesa/drivers/dri/i965/brw_state.h | 3
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 20 -
src/mesa/drivers/x11/fakeglx.c | 3
src/mesa/main/light.c | 3
src/mesa/main/mtypes.h | 3
src/mesa/program/prog_statevars.c | 2
src/util/Makefile.am | 3
src/util/SConscript | 7
src/util/disk_cache.c | 1
src/util/mesa-sha1_test.c | 65 +++
src/util/u_endian.h | 6
44 files changed, 524 insertions(+), 211 deletions(-)
New commits:
commit 4f5e85e9e97de4ae6e3d779ff42bf392c4739234
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Thu Dec 21 17:04:41 2017 +0000
docs: add release notes for 17.3.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/docs/relnotes/17.3.1.html b/docs/relnotes/17.3.1.html
new file mode 100644
index 0000000..bd1fa86
--- /dev/null
+++ b/docs/relnotes/17.3.1.html
@@ -0,0 +1,190 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 17.3.1 Release Notes / December 21, 2017</h1>
+
+<p>
+Mesa 17.3.1 is a bug fix release which fixes bugs found since the 17.3.0 release.
+</p>
+<p>
+Mesa 17.3.1 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5. OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=94739";>Bug 94739</a> - Mesa 11.1.2 implementation error: bad format MESA_FORMAT_Z_FLOAT32 in _mesa_unpack_uint_24_8_depth_stencil_row</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102710";>Bug 102710</a> - vkCmdBlitImage with arrayLayers > 1 fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103579";>Bug 103579</a> - Vertex shader causes compiler to crash in SPIRV-to-NIR</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103966";>Bug 103966</a> - Mesa 17.2.5 implementation error: bad format MESA_FORMAT_Z_FLOAT32 in _mesa_unpack_uint_24_8_depth_stencil_row</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104119";>Bug 104119</a> - radv: OpBitFieldInsert produces 0 with a loop counter for Insert</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104143";>Bug 104143</a> - r600/sb: clobbers gl_Position -> gl_FragCoord</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Alex Smith (1):</p>
+<ul>
+ <li>radv: Add LLVM version to the device name string</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (3):</p>
+<ul>
+ <li>spirv: Fix loading an entire block at once.</li>
+ <li>radv: Don't advertise VK_EXT_debug_report.</li>
+ <li>radv: Fix multi-layer blits.</li>
+</ul>
+
+<p>Ben Crocker (1):</p>
+<ul>
+ <li>docs/llvmpipe: document ppc64le as alternative architecture to x86.</li>
+</ul>
+
+<p>Brian Paul (2):</p>
+<ul>
+ <li>xlib: call _mesa_warning() instead of fprintf()</li>
+ <li>gallium/aux: include nr_samples in util_resource_size() computation</li>
+</ul>
+
+<p>Bruce Cherniak (1):</p>
+<ul>
+ <li>swr: Fix KNOB_MAX_WORKER_THREADS thread creation override.</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+ <li>radv: port merge tess info from anv</li>
+</ul>
+
+<p>Emil Velikov (5):</p>
+<ul>
+ <li>docs: add sha256 checksums for 17.3.0</li>
+ <li>util: scons: wire up the sha1 test</li>
+ <li>cherry-ignore: meson: fix strtof locale support check</li>
+ <li>cherry-ignore: util: add mesa-sha1 test to meson</li>
+ <li>Update version to 17.3.1</li>
+</ul>
+
+<p>Eric Anholt (1):</p>
+<ul>
+ <li>broadcom/vc4: Fix handling of GFXH-515 workaround with a start vertex count.</li>
+</ul>
+
+<p>Eric Engestrom (1):</p>
+<ul>
+ <li>compiler: use NDEBUG to guard asserts</li>
+</ul>
+
+<p>Fabian Bieler (2):</p>
+<ul>
+ <li>glsl: Match order of gl_LightSourceParameters elements.</li>
+ <li>glsl: Fix gl_NormalScale.</li>
+</ul>
+
+<p>Gert Wollny (1):</p>
+<ul>
+ <li>r600/sb: do not convert if-blocks that contain indirect array access</li>
+</ul>
+
+<p>James Legg (1):</p>
+<ul>
+ <li>nir/opcodes: Fix constant-folding of bitfield_insert</li>
+</ul>
+
+<p>Jason Ekstrand (1):</p>
+<ul>
+ <li>i965: Switch over to fully external-or-not MOCS scheme</li>
+</ul>
+
+<p>Juan A. Suarez Romero (1):</p>
+<ul>
+ <li>travis: disable Meson build</li>
+</ul>
+
+<p>Kenneth Graunke (2):</p>
+<ul>
+ <li>meta: Initialize depth/clear values on declaration.</li>
+ <li>meta: Fix ClearTexture with GL_DEPTH_COMPONENT.</li>
+</ul>
+
+<p>Leo Liu (1):</p>
+<ul>
+ <li>radeon/vce: move destroy command before feedback command</li>
+</ul>
+
+<p>Marek Olšák (4):</p>
+<ul>
+ <li>radeonsi: flush the context after resource_copy_region for buffer exports</li>
+ <li>radeonsi: allow DMABUF exports for local buffers</li>
+ <li>winsys/amdgpu: disable local BOs again due to worse performance</li>
+ <li>radeonsi: don't call force_dcc_off for buffers</li>
+</ul>
+
+<p>Matt Turner (2):</p>
+<ul>
+ <li>util: Assume little endian in the absence of platform-specific handling</li>
+ <li>util: Add a SHA1 unit test program</li>
+</ul>
+
+<p>Nicolai Hähnle (1):</p>
+<ul>
+ <li>radeonsi: fix the R600_RESOURCE_FLAG_UNMAPPABLE check</li>
+</ul>
+
+<p>Pierre Moreau (1):</p>
+<ul>
+ <li>nvc0/ir: Properly lower 64-bit shifts when the shift value is >32</li>
+</ul>
+
+<p>Timothy Arceri (1):</p>
+<ul>
+ <li>glsl: get correct member type when processing xfb ifc arrays</li>
+</ul>
+
+<p>Vadym Shovkoplias (2):</p>
+<ul>
+ <li>glx/dri3: Remove unused deviceName variable</li>
+ <li>util/disk_cache: Remove unneeded free() on always null string</li>
+</ul>
+
+
+</div>
+</body>
+</html>
commit 4dd13fd969c52856e59f9a091634764de5aaeab3
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Thu Dec 21 12:06:35 2017 +0000
Update version to 17.3.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/VERSION b/VERSION
index 5aadcd3..1f33a6f 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.3.0
+17.3.1
commit 09215b27b95330d887db915f0d94fe00bd9618c2
Author: Juan A. Suarez Romero <jasuarez@igalia.com>
Date: Fri Dec 15 16:03:39 2017 +0100
travis: disable Meson build
Meson is not supported in Mesa 17.3.
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/.travis.yml b/.travis.yml
index 0f42b96..87d9f15 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -364,38 +364,6 @@ matrix:
- libexpat1-dev
- libx11-xcb-dev
- libelf-dev
- - env:
- - LABEL="meson Vulkan"
- - BUILD=meson
- - MESON_OPTIONS="-Ddri-drivers= -Dgallium-drivers="
- addons:
- apt:
- sources:
- - llvm-toolchain-trusty-3.9
- packages:
- # LLVM packaging is broken and misses these dependencies
- - libedit-dev
- # From sources above
- - llvm-3.9-dev
- # Common
- - xz-utils
- - libexpat1-dev
- - libelf-dev
- - python3-pip
- - env:
- - LABEL="meson loaders/classic DRI"
- - BUILD=meson
- - MESON_OPTIONS="-Dvulkan-drivers= -Dgallium-drivers="
- addons:
- apt:
- packages:
- - xz-utils
- - x11proto-xf86vidmode-dev
- - libexpat1-dev
- - libx11-xcb-dev
- - libxdamage-dev
- - libxfixes-dev
- - python3-pip
install:
- pip install --user mako
commit a1f3f8efd9b4b1147846b39e3b69f774ac8b44b6
Author: Dave Airlie <airlied@redhat.com>
Date: Mon Dec 18 15:05:52 2017 +1000
radv: port merge tess info from anv
anv merges the tess info correctly, but radv wasn't doing this.
This fixes hangs in
dEQP-VK.tessellation.winding.default_domain.hlsl_triangles_ccw
Fixes: 60fc0544e0 (radv/pipeline: handle tessellation shader compilation)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 1bdeac545f4ea9f7ca6947f5da7fcf4f5b3010dc)
Conflicts:
src/amd/vulkan/radv_pipeline.c
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 7ad09ce..848837c 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1705,6 +1705,45 @@ radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
}
}
+static void
+merge_tess_info(struct shader_info *tes_info,
+ const struct shader_info *tcs_info)
+{
+ /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
+ *
+ * "PointMode. Controls generation of points rather than triangles
+ * or lines. This functionality defaults to disabled, and is
+ * enabled if either shader stage includes the execution mode.
+ *
+ * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
+ * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
+ * and OutputVertices, it says:
+ *
+ * "One mode must be set in at least one of the tessellation
+ * shader stages."
+ *
+ * So, the fields can be set in either the TCS or TES, but they must
+ * agree if set in both. Our backend looks at TES, so bitwise-or in
+ * the values from the TCS.
+ */
+ assert(tcs_info->tess.tcs_vertices_out == 0 ||
+ tes_info->tess.tcs_vertices_out == 0 ||
+ tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
+ tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
+
+ assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
+ tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
+ tcs_info->tess.spacing == tes_info->tess.spacing);
+ tes_info->tess.spacing |= tcs_info->tess.spacing;
+
+ assert(tcs_info->tess.primitive_mode == 0 ||
+ tes_info->tess.primitive_mode == 0 ||
+ tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
+ tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
+ tes_info->tess.ccw |= tcs_info->tess.ccw;
+ tes_info->tess.point_mode |= tcs_info->tess.point_mode;
+}
+
static
void radv_create_shaders(struct radv_pipeline *pipeline,
struct radv_device *device,
@@ -1782,6 +1821,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
+ merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
}
radv_link_shaders(pipeline, nir);
commit e1e0ce9f366c1cd79369e60367192050c1275fde
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Dec 18 15:04:37 2017 +0000
cherry-ignore: util: add mesa-sha1 test to meson
Meson is explicitly disabled in branch.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 68d200b..032d64a 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -1,2 +1,5 @@
# fixes: The commit addresses Meson which is explicitly disabled for 17.3
ab0809e5529725bd0af6f7b6ce06415020b9d32e meson: fix strtof locale support check
+
+# fixes: The commit addresses Meson which is explicitly disabled for 17.3
+44fbbd6fd07e5784b05e08e762e54b6c71f95ab1 util: add mesa-sha1 test to meson
commit ef5dbb54f69a02eb4ce91020e769c8c658402445
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Dec 18 15:03:17 2017 +0000
cherry-ignore: meson: fix strtof locale support check
Meson is explicitly disabled in branch.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
new file mode 100644
index 0000000..68d200b
--- /dev/null
+++ b/bin/.cherry-ignore
@@ -0,0 +1,2 @@
+# fixes: The commit addresses Meson which is explicitly disabled for 17.3
+ab0809e5529725bd0af6f7b6ce06415020b9d32e meson: fix strtof locale support check
commit 67d359131059aca2c1f2d90d529edcf609ec241c
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sun Dec 17 23:53:37 2017 +0100
radv: Fix multi-layer blits.
We did not set the layer correctly for the dst, as we would keep
using the base layer. Same for the source image.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102710
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit b42e106d4dfa61a6351b076741c5458b5677f332)
diff --git a/src/amd/vulkan/radv_meta_blit.c b/src/amd/vulkan/radv_meta_blit.c
index b023e0c..bbbd381 100644
--- a/src/amd/vulkan/radv_meta_blit.c
+++ b/src/amd/vulkan/radv_meta_blit.c
@@ -269,8 +269,8 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
VkOffset3D src_offset_1,
struct radv_image *dest_image,
struct radv_image_view *dest_iview,
- VkOffset3D dest_offset_0,
- VkOffset3D dest_offset_1,
+ VkOffset2D dest_offset_0,
+ VkOffset2D dest_offset_1,
VkRect2D dest_box,
VkFilter blit_filter)
{
@@ -518,21 +518,6 @@ void radv_CmdBlitImage(
for (unsigned r = 0; r < regionCount; r++) {
const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
- struct radv_image_view src_iview;
- radv_image_view_init(&src_iview, cmd_buffer->device,
- &(VkImageViewCreateInfo) {
- .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
- .image = srcImage,
- .viewType = radv_meta_get_view_type(src_image),
- .format = src_image->vk_format,
- .subresourceRange = {
- .aspectMask = src_res->aspectMask,
- .baseMipLevel = src_res->mipLevel,
- .levelCount = 1,
- .baseArrayLayer = src_res->baseArrayLayer,
- .layerCount = 1
- },
- });
unsigned dst_start, dst_end;
if (dest_image->type == VK_IMAGE_TYPE_3D) {
@@ -579,18 +564,17 @@ void radv_CmdBlitImage(
dest_box.extent.width = abs(dst_x1 - dst_x0);
dest_box.extent.height = abs(dst_y1 - dst_y0);
- struct radv_image_view dest_iview;
const unsigned num_layers = dst_end - dst_start;
for (unsigned i = 0; i < num_layers; i++) {
- const VkOffset3D dest_offset_0 = {
+ struct radv_image_view dest_iview, src_iview;
+
+ const VkOffset2D dest_offset_0 = {
.x = dst_x0,
.y = dst_y0,
- .z = dst_start + i ,
};
- const VkOffset3D dest_offset_1 = {
+ const VkOffset2D dest_offset_1 = {
.x = dst_x1,
.y = dst_y1,
- .z = dst_start + i ,
};
VkOffset3D src_offset_0 = {
.x = src_x0,
@@ -602,9 +586,10 @@ void radv_CmdBlitImage(
.y = src_y1,
.z = src_start + i * src_z_step,
};
- const uint32_t dest_array_slice =
- radv_meta_get_iview_layer(dest_image, dst_res,
- &dest_offset_0);
+ const uint32_t dest_array_slice = dst_start + i;
+
+ /* 3D images have just 1 layer */
+ const uint32_t src_array_slice = src_image->type == VK_IMAGE_TYPE_3D ? 0 : src_start + i;
radv_image_view_init(&dest_iview, cmd_buffer->device,
&(VkImageViewCreateInfo) {
@@ -620,6 +605,20 @@ void radv_CmdBlitImage(
.layerCount = 1
},
});
+ radv_image_view_init(&src_iview, cmd_buffer->device,
+ &(VkImageViewCreateInfo) {
+ .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
+ .image = srcImage,
+ .viewType = radv_meta_get_view_type(src_image),
+ .format = src_image->vk_format,
+ .subresourceRange = {
+ .aspectMask = src_res->aspectMask,
+ .baseMipLevel = src_res->mipLevel,
+ .levelCount = 1,
+ .baseArrayLayer = src_array_slice,
+ .layerCount = 1
+ },
+ });
meta_emit_blit(cmd_buffer,
src_image, &src_iview,
src_offset_0, src_offset_1,
commit 658028572b41bf09e79cd678472d3349c7418849
Author: Marek Olšák <marek.olsak@amd.com>
Date: Tue Dec 12 22:21:13 2017 +0100
radeonsi: don't call force_dcc_off for buffers
This was undefined yet harmless behavior in LLVM.
Not anymore - it causes a hang now.
Cc: 17.3 <mesa-stable@lists.freedesktop.org>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
(cherry picked from commit 35c3cbad3c30ad3d40a6811dd6ca2286e013bfc5)
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
index ec11c75..b16213c 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
@@ -146,7 +146,7 @@ LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
}
rsrc = ac_build_load_to_sgpr(&ctx->ac, list, index);
- if (dcc_off)
+ if (desc_type == AC_DESC_IMAGE && dcc_off)
rsrc = force_dcc_off(ctx, rsrc);
return rsrc;
}
commit 455ff75892a49bd2141ffeb3654fec64cd4c4143
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Thu Dec 14 17:20:30 2017 +0000
util: scons: wire up the sha1 test
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 5d03a68640dcf216484e37c316d2d91db9994a66)
diff --git a/src/util/SConscript b/src/util/SConscript
index 0c3c98a..66a0d1c 100644
--- a/src/util/SConscript
+++ b/src/util/SConscript
@@ -63,3 +63,10 @@ roundeven_test = env.Program(
source = ['roundeven_test.c'],
)
env.UnitTest("roundeven_test", roundeven_test)
+
+env.Prepend(LIBS = [mesautil])
+mesa_sha1_test = env.Program(
+ target = 'mesa-sha1_test',
+ source = ['mesa-sha1_test.c'],
+)
+env.UnitTest("mesa-sha1_test", mesa_sha1_test)
commit 60ed1a07f2991306131781cf0ec01b25f54b72c9
Author: Matt Turner <mattst88@gmail.com>
Date: Wed Nov 22 15:10:47 2017 -0800
util: Add a SHA1 unit test program
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 513d7ffa23d42e96f831148fa13bf470087424c3)
diff --git a/src/util/Makefile.am b/src/util/Makefile.am
index b57da3c..a5241ad 100644
--- a/src/util/Makefile.am
+++ b/src/util/Makefile.am
@@ -68,8 +68,9 @@ sysconf_DATA = drirc
u_atomic_test_LDADD = libmesautil.la
roundeven_test_LDADD = -lm
+mesa_sha1_test_LDADD = libmesautil.la
-check_PROGRAMS = u_atomic_test roundeven_test
+check_PROGRAMS = u_atomic_test roundeven_test mesa-sha1_test
TESTS = $(check_PROGRAMS)
BUILT_SOURCES = $(MESA_UTIL_GENERATED_FILES)
diff --git a/src/util/mesa-sha1_test.c b/src/util/mesa-sha1_test.c
new file mode 100644
index 0000000..9b3b477
--- /dev/null
+++ b/src/util/mesa-sha1_test.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <stdbool.h>
+#include <string.h>
+
+#include "macros.h"
+#include "mesa-sha1.h"
+
+#define SHA1_LENGTH 40
+
+int main(int argc, char *argv[])
+{
+ static const struct {
+ const char *string;
+ const char *sha1;
+ } test_data[] = {
+ {"Mesa Rocks! 273", "7fb99737373d65a73f049cdabc01e73aa6bc60f3"},
+ {"Mesa Rocks! 300", "b2180263e37d3bed6a4be0afe41b1a82ebbcf4c3"},
+ {"Mesa Rocks! 583", "7fb9734108a62503e8a149c1051facd7fb112d05"},
+ };
+
+ bool failed = false;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(test_data); i++) {
+ unsigned char sha1[20];
+ _mesa_sha1_compute(test_data[i].string, strlen(test_data[i].string),
+ sha1);
+
+ char buf[41];
+ _mesa_sha1_format(buf, sha1);
+
+ if (memcmp(test_data[i].sha1, buf, SHA1_LENGTH) != 0) {
+ printf("For string \"%s\", length %zu:\n"
+ "\tExpected: %s\n\t Got: %s\n",
+ test_data[i].string, strlen(test_data[i].string),
+ test_data[i].sha1, buf);
+ failed = true;
+ }
+ }
+
+ return failed;
+}
commit 9a49b36368e3c5e03610ac8c37ab2af9fa0c769d
Author: Matt Turner <mattst88@gmail.com>
Date: Fri Nov 24 20:25:04 2017 -0800
util: Assume little endian in the absence of platform-specific handling
(cherry picked from commit 6a353479a7577dcff7c7a31809f27b59270648fb)
Squashed with:
util: Use preprocessor correctly
Fixes: 6a353479a757 ("util: Assume little endian in the absence of
platform-specific handling")
(cherry picked from commit b8cbad624b8198949d63c0211fe4925fc3bb9a7a)
Squashed with:
util: Just give up and define PIPE_ARCH_LITTLE_ENDIAN on MSVC
MSVC doesn't support #warning?! Getting really tired of this.
(cherry picked from commit 676761252b731a6bf408e4dca694c31d74a995fc)
Squashed with:
util: Also include endian.h on cygwin
If u_endian.h can't determine the endianess, the default behaviour in sha1.c
is to build for big-endian
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 2c62ccb10a7f3a2962f51688a3ae957254c5ce9b)
diff --git a/src/util/u_endian.h b/src/util/u_endian.h
index b9d563d..9e09f80 100644
--- a/src/util/u_endian.h
+++ b/src/util/u_endian.h
@@ -27,7 +27,7 @@
#ifndef U_ENDIAN_H
#define U_ENDIAN_H
-#if defined(__GLIBC__) || defined(ANDROID)
+#if defined(__GLIBC__) || defined(ANDROID) || defined(__CYGWIN__)
#include <endian.h>
#if __BYTE_ORDER == __LITTLE_ENDIAN
@@ -64,6 +64,10 @@
# define PIPE_ARCH_BIG_ENDIAN
#endif
+#elif defined(_MSC_VER)
+
+#define PIPE_ARCH_LITTLE_ENDIAN
+
#endif
#endif
commit 4b4d8dad71f815649e8df3fcc0976f52ff2a7ae1
Author: Eric Anholt <eric@anholt.net>
Date: Fri Nov 24 21:40:50 2017 -0800
broadcom/vc4: Fix handling of GFXH-515 workaround with a start vertex count.
We failed to take the start into account for how many vertices to draw in
this round, so we would end up decrementing count below 0, which as an
unsigned number meant we would loop until the CLs soon ran out of space.
When I wrote the code I was thinking about how to use the previously
emitted shader state (no index bias baked into the elements) by emitting
up to 65535 and then only re-emitting with bias for the second wround, but
that doesn't work if the start is over 65535. Instead, just delay
emitting shader state until we get into the drawarrays GFXH-515 loop and
always bake the bias in when we're doing the workaround.
(cherry picked from commit 84ab48c15c9373dfa4709f4f9e887c329286e5a1)
diff --git a/src/gallium/drivers/vc4/vc4_draw.c b/src/gallium/drivers/vc4/vc4_draw.c
index 9522bb9..5568554 100644
--- a/src/gallium/drivers/vc4/vc4_draw.c
+++ b/src/gallium/drivers/vc4/vc4_draw.c
@@ -331,6 +331,7 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
vc4_emit_state(pctx);
+ bool needs_drawarrays_shader_state = false;
if ((vc4->dirty & (VC4_DIRTY_VTXBUF |
VC4_DIRTY_VTXSTATE |
VC4_DIRTY_PRIM_MODE |
@@ -342,7 +343,10 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
vc4->prog.vs->uniform_dirty_bits |
vc4->prog.fs->uniform_dirty_bits)) ||
vc4->last_index_bias != info->index_bias) {
- vc4_emit_gl_shader_state(vc4, info, 0);
+ if (info->index_size)
+ vc4_emit_gl_shader_state(vc4, info, 0);
+ else
+ needs_drawarrays_shader_state = true;
}
vc4->dirty = 0;
@@ -392,29 +396,35 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
uint32_t count = info->count;
uint32_t start = info->start;
uint32_t extra_index_bias = 0;
+ static const uint32_t max_verts = 65535;
+
+ /* GFXH-515 / SW-5891: The binner emits 16 bit indices for
+ * drawarrays, which means that if start + count > 64k it
+ * would truncate the top bits. Work around this by emitting
+ * a limited number of primitives at a time and reemitting the
+ * shader state pointing farther down the vertex attribute
+ * arrays.
+ *
+ * To do this properly for line loops or trifans, we'd need to
+ * make a new VB containing the first vertex plus whatever
+ * remainder.
+ */
+ if (start + count > max_verts) {
+ extra_index_bias = start;
+ start = 0;
+ needs_drawarrays_shader_state = true;
+ }
while (count) {
uint32_t this_count = count;
uint32_t step = count;
- static const uint32_t max_verts = 65535;
-
- /* GFXH-515 / SW-5891: The binner emits 16 bit indices
- * for drawarrays, which means that if start + count >
- * 64k it would truncate the top bits. Work around
- * this by emitting a limited number of primitives at
- * a time and reemitting the shader state pointing
- * farther down the vertex attribute arrays.
- *
- * To do this properly for line loops or trifans, we'd
- * need to make a new VB containing the first vertex
- * plus whatever remainder.
- */
- if (extra_index_bias) {
+
+ if (needs_drawarrays_shader_state) {
vc4_emit_gl_shader_state(vc4, info,
extra_index_bias);
}
- if (start + count > max_verts) {
+ if (count > max_verts) {
switch (info->mode) {
case PIPE_PRIM_POINTS:
this_count = step = max_verts;
@@ -457,6 +467,7 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
count -= step;
extra_index_bias += start + step;
start = 0;
+ needs_drawarrays_shader_state = true;
}
}
commit 77148639d35d7f7c8d9dddafbb40969c2de819e7
Author: Fabian Bieler <fabianbieler@fastmail.fm>
Date: Thu Nov 23 13:48:00 2017 -0700
glsl: Fix gl_NormalScale.
GLSL shaders can access the normal scale factor with the built-in
gl_NormalScale. Mesa's modelspace lighting optimization uses a different
normal scale factor than defined in the spec. We have to take care not
to use this factor for gl_NormalScale.
Mesa already defines two seperate states: state.normalScale and
state.internal.normalScale. The first is used by the glsl compiler
while the later is used by the fixed function T&L pipeline. Previously
the only difference was some component swizzling. With this commit
state.normalScale always uses the normal scale factor for eyespace
lighting.
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit c3ee464d7aa170225b5ec23b53a7f8d07663d428)
diff --git a/src/mesa/main/light.c b/src/mesa/main/light.c
index f52ed8e..67faf8a 100644
--- a/src/mesa/main/light.c
+++ b/src/mesa/main/light.c
@@ -1032,6 +1032,7 @@ static void
update_modelview_scale( struct gl_context *ctx )
{
ctx->_ModelViewInvScale = 1.0F;
+ ctx->_ModelViewInvScaleEyespace = 1.0F;
if (!_math_matrix_is_length_preserving(ctx->ModelviewMatrixStack.Top)) {
const GLfloat *m = ctx->ModelviewMatrixStack.Top->inv;
GLfloat f = m[2] * m[2] + m[6] * m[6] + m[10] * m[10];
@@ -1040,6 +1041,7 @@ update_modelview_scale( struct gl_context *ctx )
ctx->_ModelViewInvScale = 1.0f / sqrtf(f);
else
ctx->_ModelViewInvScale = sqrtf(f);
+ ctx->_ModelViewInvScaleEyespace = 1.0f / sqrtf(f);
}
}
@@ -1216,4 +1218,5 @@ _mesa_init_lighting( struct gl_context *ctx )
ctx->_NeedEyeCoords = GL_FALSE;
ctx->_ForceEyeCoords = GL_FALSE;
ctx->_ModelViewInvScale = 1.0;
+ ctx->_ModelViewInvScaleEyespace = 1.0;
}
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 2c44883..216bbc4 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -4935,7 +4935,8 @@ struct gl_context
/** \name Derived state */
GLbitfield _ImageTransferState;/**< bitwise-or of IMAGE_*_BIT flags */
GLfloat _EyeZDir[3];
- GLfloat _ModelViewInvScale;
+ GLfloat _ModelViewInvScale; /* may be for model- or eyespace lighting */
+ GLfloat _ModelViewInvScaleEyespace; /* always factor defined in spec */
GLboolean _NeedEyeCoords;
GLboolean _ForceEyeCoords;
diff --git a/src/mesa/program/prog_statevars.c b/src/mesa/program/prog_statevars.c
index 91178e3..b69895c 100644
--- a/src/mesa/program/prog_statevars.c
+++ b/src/mesa/program/prog_statevars.c
@@ -422,7 +422,7 @@ _mesa_fetch_state(struct gl_context *ctx, const gl_state_index state[],
return;
case STATE_NORMAL_SCALE:
- ASSIGN_4V(value, ctx->_ModelViewInvScale, 0, 0, 1);
+ ASSIGN_4V(value, ctx->_ModelViewInvScaleEyespace, 0, 0, 1);
return;
case STATE_INTERNAL:
commit 140c735963d6849e4bd89f760c6d33a00726bb44
Author: Fabian Bieler <fabianbieler@fastmail.fm>
Date: Thu Nov 23 13:48:00 2017 -0700
glsl: Match order of gl_LightSourceParameters elements.
spotExponent and spotCosCutoff were swapped in the
gl_builtin_uniform_element struct.
Now the order matches across gl_builtin_uniform_element,
glsl_struct_field and the spec.
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit 9bdb5457f4ecabd59e05d0b6cea1ff88bcb49d7f)
diff --git a/src/compiler/glsl/builtin_variables.cpp b/src/compiler/glsl/builtin_variables.cpp
index 00bc99d..a885f32 100644
--- a/src/compiler/glsl/builtin_variables.cpp
+++ b/src/compiler/glsl/builtin_variables.cpp
@@ -90,9 +90,9 @@ static const struct gl_builtin_uniform_element gl_LightSource_elements[] = {
SWIZZLE_Y,
SWIZZLE_Z,
SWIZZLE_Z)},
- {"spotCosCutoff", {STATE_LIGHT, 0, STATE_SPOT_DIRECTION}, SWIZZLE_WWWW},
- {"spotCutoff", {STATE_LIGHT, 0, STATE_SPOT_CUTOFF}, SWIZZLE_XXXX},
{"spotExponent", {STATE_LIGHT, 0, STATE_ATTENUATION}, SWIZZLE_WWWW},
+ {"spotCutoff", {STATE_LIGHT, 0, STATE_SPOT_CUTOFF}, SWIZZLE_XXXX},
+ {"spotCosCutoff", {STATE_LIGHT, 0, STATE_SPOT_DIRECTION}, SWIZZLE_WWWW},
{"constantAttenuation", {STATE_LIGHT, 0, STATE_ATTENUATION}, SWIZZLE_XXXX},
{"linearAttenuation", {STATE_LIGHT, 0, STATE_ATTENUATION}, SWIZZLE_YYYY},
{"quadraticAttenuation", {STATE_LIGHT, 0, STATE_ATTENUATION}, SWIZZLE_ZZZZ},
commit c798b07981aba2e48561a7c1d51c04d300123b54
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Mon Nov 13 20:13:09 2017 -0800
i965: Switch over to fully external-or-not MOCS scheme
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 4b1e70cc57d7ff5f465544644b2180dee1490cee)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 626bf44..38284d3 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -114,20 +114,6 @@ brw_blorp_init(struct brw_context *brw)
brw->blorp.upload_shader = brw_blorp_upload_shader;
}
-static uint32_t wb_mocs[] = {
- [7] = GEN7_MOCS_L3,
- [8] = BDW_MOCS_WB,
- [9] = SKL_MOCS_WB,
- [10] = CNL_MOCS_WB,
-};
-
-static uint32_t pte_mocs[] = {
- [7] = GEN7_MOCS_L3,
- [8] = BDW_MOCS_PTE,
- [9] = SKL_MOCS_PTE,
- [10] = CNL_MOCS_PTE,
-};
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