mesa: Changes to 'upstream-experimental'
VERSION | 2
src/amd/common/ac_nir_to_llvm.c | 6
src/amd/common/ac_surface.c | 32 +
src/amd/vulkan/radv_device.c | 9
src/amd/vulkan/radv_pipeline.c | 17 -
src/amd/vulkan/radv_pipeline_cache.c | 2
src/amd/vulkan/radv_shader.c | 3
src/compiler/Makefile.sources | 1
src/compiler/glsl/builtin_variables.cpp | 94 -----
src/compiler/glsl/glsl_parser_extras.cpp | 2
src/compiler/glsl/ir.h | 4
src/compiler/glsl/ir_optimization.h | 1
src/compiler/glsl/linker.cpp | 3
src/compiler/glsl/lower_cs_derived.cpp | 234 ++++++++++++++
src/compiler/glsl/meson.build | 1
src/compiler/glsl/opt_dead_builtin_variables.cpp | 22 -
src/compiler/nir/nir_intrinsics.h | 2
src/compiler/spirv/spirv_to_nir.c | 3
src/egl/meson.build | 9
src/egl/wayland/wayland-egl/Makefile.am | 2
src/egl/wayland/wayland-egl/meson.build | 1
src/gallium/drivers/radeon/radeon_video.c | 5
src/gallium/drivers/radeonsi/driinfo_radeonsi.h | 2
src/gallium/drivers/radeonsi/si_blit.c | 10
src/gallium/drivers/radeonsi/si_pipe.c | 4
src/gallium/drivers/radeonsi/si_pipe.h | 2
src/gallium/drivers/radeonsi/si_shader.c | 13
src/gallium/drivers/vc4/vc4_cl.h | 12
src/gallium/state_trackers/clover/llvm/codegen/common.cpp | 5
src/gallium/state_trackers/clover/llvm/compat.hpp | 12
src/intel/compiler/brw_eu_emit.c | 2
src/intel/compiler/brw_eu_validate.c | 3
src/intel/compiler/brw_fs.cpp | 4
src/intel/compiler/brw_fs_generator.cpp | 1
src/intel/vulkan/anv_pipeline.c | 3
src/mesa/drivers/dri/i965/brw_blorp.c | 26 -
src/mesa/drivers/dri/i965/brw_context.c | 6
src/mesa/drivers/dri/i965/brw_draw.c | 13
src/mesa/drivers/dri/i965/brw_state_upload.c | 24 -
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 13
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 23 -
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 9
src/mesa/drivers/dri/i965/intel_screen.c | 2
src/mesa/main/bufferobj.c | 6
src/mesa/main/fbobject.c | 9
src/util/drirc | 2
src/util/xmlpool/t_options.h | 6
47 files changed, 425 insertions(+), 242 deletions(-)
New commits:
commit 3eb187f3760866143a9aebe904aefa0e7b0105aa
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Oct 30 13:52:46 2017 +0000
Update version to 17.3.0-rc2
diff --git a/VERSION b/VERSION
index dd84678..00ea172 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.3.0-rc1
+17.3.0-rc2
commit 0c20849f9c30864d5aa183aaf7075916bb7ea4f2
Author: Eric Engestrom <eric.engestrom@imgtec.com>
Date: Thu Oct 26 17:13:47 2017 +0100
wayland-egl: fix wayland cflags
Fixes: 80bfff5c4f1d4d8c842a0 "wayland-egl: adds CFLAGS for wayland.egl.h include"
Suggested-by: Daniel Stone <daniel@fooishbar.org>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
(cherry picked from commit 866c8a94d45fd88ea1e3a49c00a0ee5e589e4577)
diff --git a/src/egl/wayland/wayland-egl/Makefile.am b/src/egl/wayland/wayland-egl/Makefile.am
index 730fd03..7dde955 100644
--- a/src/egl/wayland/wayland-egl/Makefile.am
+++ b/src/egl/wayland/wayland-egl/Makefile.am
@@ -3,7 +3,7 @@ pkgconfig_DATA = wayland-egl.pc
AM_CFLAGS = $(DEFINES) \
$(VISIBILITY_CFLAGS) \
- $(WAYLAND_SERVER_CFLAGS)
+ $(WAYLAND_CLIENT_CFLAGS)
lib_LTLIBRARIES = libwayland-egl.la
noinst_HEADERS = wayland-egl-backend.h
commit fb09360ea51140ef84f5516ae668299d7a48cc77
Author: Eric Engestrom <eric.engestrom@imgtec.com>
Date: Wed Oct 25 14:08:58 2017 +0100
vc4: fix release build
Mesa's DEBUG and assert's NDEBUG are not tied to each other, so we need
to explicitly compile this code out.
Fixes: 3df78928786134874eafa "vc4: Drop reloc_count tracking for debug
asserts on non-debug builds."
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 5d44e35a8f3967b40db153fdcedb9294d44ae5c4)
diff --git a/src/gallium/drivers/vc4/vc4_cl.h b/src/gallium/drivers/vc4/vc4_cl.h
index 0361326..8df9dbf 100644
--- a/src/gallium/drivers/vc4/vc4_cl.h
+++ b/src/gallium/drivers/vc4/vc4_cl.h
@@ -61,7 +61,7 @@ struct vc4_cl {
struct vc4_cl_out *next;
struct vc4_cl_out *reloc_next;
uint32_t size;
-#ifdef DEBUG
+#ifndef NDEBUG
uint32_t reloc_count;
#endif
};
@@ -163,8 +163,8 @@ static inline void
cl_start_reloc(struct vc4_cl *cl, struct vc4_cl_out **out, uint32_t n)
{
assert(n == 1 || n == 2);
-#ifdef DEBUG
assert(cl->reloc_count == 0);
+#ifndef NDEBUG
cl->reloc_count = n;
#endif
@@ -177,8 +177,8 @@ cl_start_reloc(struct vc4_cl *cl, struct vc4_cl_out **out, uint32_t n)
static inline struct vc4_cl_out *
cl_start_shader_reloc(struct vc4_cl *cl, uint32_t n)
{
-#ifdef DEBUG
assert(cl->reloc_count == 0);
+#ifndef NDEBUG
cl->reloc_count = n;
#endif
cl->reloc_next = cl->next;
@@ -196,7 +196,7 @@ cl_reloc(struct vc4_job *job, struct vc4_cl *cl, struct vc4_cl_out **cl_out,
*(uint32_t *)cl->reloc_next = vc4_gem_hindex(job, bo);
cl_advance(&cl->reloc_next, 4);
-#ifdef DEBUG
+#ifndef NDEBUG
cl->reloc_count--;
#endif
@@ -211,7 +211,7 @@ cl_aligned_reloc(struct vc4_job *job, struct vc4_cl *cl,
*(uint32_t *)cl->reloc_next = vc4_gem_hindex(job, bo);
cl_advance(&cl->reloc_next, 4);
-#ifdef DEBUG
+#ifndef NDEBUG
cl->reloc_count--;
#endif
@@ -297,7 +297,7 @@ cl_pack_emit_reloc(struct vc4_cl *cl, const struct vc4_cl_reloc *reloc)
*(uint32_t *)cl->reloc_next = vc4_gem_hindex(cl->job, reloc->bo);
cl_advance(&cl->reloc_next, 4);
-#ifdef DEBUG
+#ifndef NDEBUG
cl->reloc_count--;
#endif
}
commit 166432283814507a1b69d0546b32dfcd0b107474
Author: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Thu Oct 26 18:08:19 2017 +0200
radeonsi: update hack for HTILE corruption in ARK: Survival Evolved
It appears that flushing the DB metadata is actually not sufficient
since the driver uses the new VS blit shaders. This looks quite
strange though, but it seems like we need to flush DB for fixing
the corruption.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102955
Fixes: 69ccb9dae7 (radeonsi: use new VS blit shaders (VS inputs in SGPRs)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit dd79aa4ad30df205076be25f6bbf42768abea20a)
diff --git a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
index 402d340..7f57b4e 100644
--- a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
+++ b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
@@ -6,5 +6,5 @@ DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
- DRI_CONF_RADEONSI_CLEAR_DB_META_BEFORE_CLEAR("false")
+ DRI_CONF_RADEONSI_CLEAR_DB_CACHE_BEFORE_CLEAR("false")
DRI_CONF_SECTION_END
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index fd8559a..abf25b6 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -901,16 +901,16 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
* corruption in ARK: Survival Evolved, but that may just be
* a coincidence and the root cause is elsewhere.
*
- * The corruption can be fixed by putting the DB metadata flush
- * before or after the depth clear. (suprisingly)
+ * The corruption can be fixed by putting the DB flush before
+ * or after the depth clear. (surprisingly)
*
* https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
*
* This hack decreases back-to-back ClearDepth performance.
*/
- if (sctx->screen->clear_db_meta_before_clear)
- sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META |
- SI_CONTEXT_PS_PARTIAL_FLUSH;
+ if (sctx->screen->clear_db_cache_before_clear) {
+ sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
+ }
}
si_blitter_begin(ctx, SI_CLEAR);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 759d539..a6c3aa0 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1072,8 +1072,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
sscreen->commutative_blend_add =
driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
- sscreen->clear_db_meta_before_clear =
- driQueryOptionb(config->options, "radeonsi_clear_db_meta_before_clear");
+ sscreen->clear_db_cache_before_clear =
+ driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
sscreen->b.family <= CHIP_POLARIS12) ||
sscreen->b.family == CHIP_VEGA10 ||
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index c162a0f..8d7703b 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -98,7 +98,7 @@ struct si_screen {
bool has_out_of_order_rast;
bool assume_no_z_fights;
bool commutative_blend_add;
- bool clear_db_meta_before_clear;
+ bool clear_db_cache_before_clear;
bool has_msaa_sample_loc_bug;
bool dpbb_allowed;
bool dfsm_allowed;
diff --git a/src/util/drirc b/src/util/drirc
index 39ac3c8..05630eb 100644
--- a/src/util/drirc
+++ b/src/util/drirc
@@ -264,7 +264,7 @@ TODO: document the other workarounds.
</device>
<device driver="radeonsi">
<application name="ARK: Survival Evolved (and unintentionally the UE4 demo template)" executable="ShooterGame">
- <option name="radeonsi_clear_db_meta_before_clear" value="true" />
+ <option name="radeonsi_clear_db_cache_before_clear" value="true" />
</application>
</device>
</driconf>
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index 957ed61..41f6ebd 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -444,7 +444,7 @@ DRI_CONF_OPT_BEGIN_B(radeonsi_commutative_blend_add, def) \
DRI_CONF_DESC(en,gettext("Commutative additive blending optimizations (may cause rendering errors)")) \
DRI_CONF_OPT_END
-#define DRI_CONF_RADEONSI_CLEAR_DB_META_BEFORE_CLEAR(def) \
-DRI_CONF_OPT_BEGIN_B(radeonsi_clear_db_meta_before_clear, def) \
- DRI_CONF_DESC(en,"Clear DB metadata cache before fast depth clear") \
+#define DRI_CONF_RADEONSI_CLEAR_DB_CACHE_BEFORE_CLEAR(def) \
+DRI_CONF_OPT_BEGIN_B(radeonsi_clear_db_cache_before_clear, def) \
+ DRI_CONF_DESC(en,"Clear DB cache before fast depth clear") \
DRI_CONF_OPT_END
commit c7e625df6966588c4e71a8d13e147792a76215b2
Author: Daniel Stone <daniels@collabora.com>
Date: Thu Oct 26 11:56:22 2017 +0100
meson: wayland-egl depends on wayland-client
Since wayland-egl.h is currently provided by the core Wayland package,
depend on wayland-client to make sure we get it in our include path.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Fixes: 108d257a16 ("meson: build libEGL")
Cc: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Cc: Dylan Baker <dylan@pnwbakers.com>
Cc: Gert Wollny <gw.fossdev@gmail.com>
(cherry picked from commit 9f7ed60b3eae9d3d20805e79c9ab67674619e2cd)
diff --git a/src/egl/wayland/wayland-egl/meson.build b/src/egl/wayland/wayland-egl/meson.build
index 5e7c310..f380e96 100644
--- a/src/egl/wayland/wayland-egl/meson.build
+++ b/src/egl/wayland/wayland-egl/meson.build
@@ -24,6 +24,7 @@ libwayland_egl = shared_library(
'wayland-egl.c',
c_args : [c_vis_args],
link_args : ld_args_gc_sections,
+ dependencies : dep_wayland_client,
version : '1.0.0',
install : true,
)
commit 5addf041efe3f5874bbcfa1a950f25f2b192bbf0
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Thu Aug 31 11:42:00 2017 -0700
intel/eu: Use EXECUTE_1 for JMPI
The PRM says "The execution size must be 1." In 73137997e23ff6c11, the
execution size was set to 1 when it should have been BRW_EXECUTE_1
(which maps to 0). Later, in dc2d3a7f5c217a7cee9, JMPI was used for
line AA on gen6 and earlier and we started manually stomping the
exeution size to BRW_EXECUTE_1 in the generator. This commit fixes the
original bug and makes brw_JMPI just do the right thing.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: 73137997e23ff6c1145d036315d1a9ad96651281
(cherry picked from commit 562b8d458c2de262019da2c056f75cb9feb5ee54)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 062c631..4f0be55 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -1190,7 +1190,7 @@ brw_JMPI(struct brw_codegen *p, struct brw_reg index,
struct brw_reg ip = brw_ip_reg();
brw_inst *inst = brw_alu2(p, BRW_OPCODE_JMPI, ip, ip, index);
- brw_inst_set_exec_size(devinfo, inst, BRW_EXECUTE_2);
+ brw_inst_set_exec_size(devinfo, inst, BRW_EXECUTE_1);
brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
brw_inst_set_mask_control(devinfo, inst, BRW_MASK_DISABLE);
brw_inst_set_pred_control(devinfo, inst, predicate_control);
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index bdf2f91..0558c82 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -402,7 +402,6 @@ fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
- brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
{
/* Don't send AA data */
fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
commit f4b6883ebc8802d82c2389361b852088b76c00b7
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Wed Oct 25 03:43:00 2017 +0200
radv: Fix truncation issue hexifying the cache uuid for the disk cache.
Going from binary to hex has a 2x blowup.
Fixes: 14216252923 'radv: create on-disk shader cache'
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 5bfbab2fdcc5b1fcb3a0d0b8cce19c5492c7de68)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index ebc74fb..19ff8fe 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -170,8 +170,8 @@ radv_physical_device_init(struct radv_physical_device *device,
/* The gpu id is already embeded in the uuid so we just pass "radv"
* when creating the cache.
*/
- char buf[VK_UUID_SIZE + 1];
- disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE);
+ char buf[VK_UUID_SIZE * 2 + 1];
+ disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
commit 70ee0a45250c4121b800843d1f5c3c66b78988ff
Author: Eric Anholt <eric@anholt.net>
Date: Tue Oct 17 15:41:25 2017 -0700
i965: Fix memmem compiler warnings.
gcc is throwing this warning in my meson build:
../src/intel/compiler/brw_eu_validate.c:50:11: warning
argument 1 null where non-null expected [-Wnonnull]
return memmem(haystack.str, haystack.len,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
needle.str, needle.len) != NULL;
~~~~~~~~~~~~~~~~~~~~~~~
The first check for CONTAINS has a NULL error_msg.str and 0 len. The
glibc implementation will exit without looking at any haystack bytes if
haystack.len < needle.len, so this was safe, but silence the warning
anyway by guarding against implementation variablility.
Fixes: 122ef3799d56 ("i965: Only insert error message if not already present")
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit e91c3540fc620b39a16d5bce9fd75aa0ddd7ed7e)
diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c
index 9f72c65..f359599 100644
--- a/src/intel/compiler/brw_eu_validate.c
+++ b/src/intel/compiler/brw_eu_validate.c
@@ -47,7 +47,8 @@ cat(struct string *dest, const struct string src)
static bool
contains(const struct string haystack, const struct string needle)
{
- return memmem(haystack.str, haystack.len, needle.str, needle.len) != NULL;
+ return haystack.str && memmem(haystack.str, haystack.len,
+ needle.str, needle.len) != NULL;
}
#define CONTAINS(haystack, needle) \
contains(haystack, (struct string){needle, strlen(needle)})
commit 17d988bfaab755cd4076224b199e9ca56eb68614
Author: Timothy Arceri <tarceri@itsqueeze.com>
Date: Tue Oct 24 09:08:55 2017 +1100
radv: move nir print after linking is done
We now have linking optimisations so we want to delay dumping the
nir until after these are complete.
Fixes: 06f05040eb73 (radv: Link shaders)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit f0a2bbd1a4a0caf85d91469e61d01a126cfc2a36)
Squashed with commit:
radv: print NIR before LLVM IR and disassembly
It's still printed after linking, but it makes more sense to
have SPIRV->NIR->LLVM IR->ASM.
Fixes: f0a2bbd1a4 (radv: move nir print after linking is done)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 9711979df007859de86fc08c20c826a71d10a660)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 30a90ac..7ad09ce 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1786,6 +1786,14 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
radv_link_shaders(pipeline, nir);
+ for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
+ if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
+ continue;
+
+ if (modules[i])
+ nir_print_shader(nir[i], stderr);
+ }
+
if (nir[MESA_SHADER_FRAGMENT]) {
if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
pipeline->shaders[MESA_SHADER_FRAGMENT] =
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 6176a2e..5903917 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -291,9 +291,6 @@ radv_shader_compile_to_nir(struct radv_device *device,
nir_remove_dead_variables(nir, nir_var_local);
radv_optimize_nir(nir);
- if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)
- nir_print_shader(nir, stderr);
-
return nir;
}
commit 03cf1953ad1ac067abe14642e9ea1bb725ba31b8
Author: Dave Airlie <airlied@redhat.com>
Date: Mon Oct 23 10:34:54 2017 +1000
mesa/bufferobj: don't double negate the range
This fixes a regression I introduced refactoring this code,
I managed to invert range twice, I moved the inversion into
the common code, but forgot to stop doing it in the callee.
Fixes: GL45-CTS.multi_bind.dispatch_bind_buffers_base
Fixes: 35ac13ed3 (mesa/bufferobj: consolidate some codepaths between ubo/ssbo/atomics.)
Reported-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 11d688d9f0d2ee4d0178d1807c0075e5e8364b1d)
diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index b7a9692..dfeea94 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -3815,7 +3815,7 @@ bind_uniform_buffers(struct gl_context *ctx, GLuint first, GLsizei count,
}
set_buffer_multi_binding(ctx, buffers, i, caller,
- binding, offset, size, !range,
+ binding, offset, size, range,
USAGE_UNIFORM_BUFFER);
}
@@ -3916,7 +3916,7 @@ bind_shader_storage_buffers(struct gl_context *ctx, GLuint first,
}
set_buffer_multi_binding(ctx, buffers, i, caller,
- binding, offset, size, !range,
+ binding, offset, size, range,
USAGE_SHADER_STORAGE_BUFFER);
}
@@ -4238,7 +4238,7 @@ bind_atomic_buffers(struct gl_context *ctx,
}
set_buffer_multi_binding(ctx, buffers, i, caller,
- binding, offset, size, !range,
+ binding, offset, size, range,
USAGE_ATOMIC_COUNTER_BUFFER);
}
commit 4fb6b83968f235ea727b55d366e4f412df148c49
Author: Timothy Arceri <tarceri@itsqueeze.com>
Date: Mon Oct 23 11:10:47 2017 +1100
radv: clone meta shaders before linking
The IR is reused in different pipeline combinations so we need
to clone it to avoid link time optimistaions messing up the
original copy.
Fixes: 06f05040eb73 (radv: Link shaders)
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 013313cf895e4d47b2631d5f4dd32fcbce2b0a17)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 669d9a4..30a90ac 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1766,6 +1766,13 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
stage ? stage->pName : "main", i,
stage ? stage->pSpecializationInfo : NULL);
pipeline->active_stages |= mesa_to_vk_shader_stage(i);
+ /* We don't want to alter meta shaders IR directly so clone it
+ * first.
+ */
+ if (nir[i]->info.name) {
+ nir[i] = nir_shader_clone(NULL, nir[i]);
+ }
+
}
if (nir[MESA_SHADER_TESS_CTRL]) {
@@ -1863,7 +1870,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
free(codes[i]);
- if (modules[i] && !modules[i]->nir && !pipeline->device->trace_bo)
+ if (modules[i] && !pipeline->device->trace_bo)
ralloc_free(nir[i]);
}
commit 26b44eadac90187b7c0d3fdb21c218d08b657df6
Author: Dylan Baker <dylan@pnwbakers.com>
Date: Fri Oct 20 17:34:51 2017 -0700
meson: fix egl build for meson version < 0.43
Meson 0.43 added the ability to pass nested lists to
include_directories, so the code that we have works for 0.43, but not
for 0.42. This patch changes the include_directories list to be flat so
it works with 0.42
fixes: 108d257a16859898f5c ("meson: build libEGL")
Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
(cherry picked from commit 77f7ef0287cee23d411b1a2e750d281efe425ff3)
diff --git a/src/egl/meson.build b/src/egl/meson.build
index 8ea8a5b..ea7ae06 100644
--- a/src/egl/meson.build
+++ b/src/egl/meson.build
@@ -21,7 +21,9 @@
c_args_for_egl = []
link_for_egl = []
deps_for_egl = []
-incs_for_egl = []
+incs_for_egl = [
+ inc_include, inc_src, inc_loader, inc_gbm, include_directories('main'),
+]
files_egl = files(
'main/eglapi.c',
'main/eglapi.h',
@@ -159,10 +161,7 @@ libegl = shared_library(
'-D_EGL_BUILT_IN_DRIVER_DRI2',
'-D_EGL_NATIVE_PLATFORM=_EGL_PLATFORM_@0@'.format(egl_native_platform.to_upper()),
],
- include_directories : [
- incs_for_egl, inc_include, inc_src, inc_loader, inc_gbm,
- include_directories('main'),
- ],
+ include_directories : incs_for_egl,
link_with : [link_for_egl, libloader, libxmlconfig, libglapi, libmesa_util],
link_args : [ld_args_bsymbolic, ld_args_gc_sections],
dependencies : [deps_for_egl, dep_dl, dep_libdrm, dep_clock, dep_thread],
commit e22cf6e9b4cb3823f5b8115d8c7cfd6deae75006
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Thu Oct 26 11:44:09 2017 -0700
mesa: Accept GL_BACK in get_fb0_attachment with ARB_ES3_1_compatibility.
According to the ARB_ES3_1_compatibility specification,
glGetFramebufferAttachmentParameteriv is supposed to accept BACK,
and it behaves exactly like BACK_LEFT.
Fixes a GL error in GFXBench 5 Aztec Ruins.
Cc: "17.3 17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit 4f538c3f99b25dc96cd20314ce7785fd4d333be1)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index 71e91f9..9a2c7eb 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -330,6 +330,15 @@ get_fb0_attachment(struct gl_context *ctx, struct gl_framebuffer *fb,
return &fb->Attachment[BUFFER_BACK_LEFT];
case GL_BACK_RIGHT:
return &fb->Attachment[BUFFER_BACK_RIGHT];
+ case GL_BACK:
+ /* The ARB_ES3_1_compatibility spec says:
+ *
+ * "Since this command can only query a single framebuffer
+ * attachment, BACK is equivalent to BACK_LEFT."
+ */
+ if (ctx->Extensions.ARB_ES3_1_compatibility)
+ return &fb->Attachment[BUFFER_BACK_LEFT];
+ return NULL;
case GL_AUX0:
if (fb->Visual.numAuxBuffers == 1) {
return &fb->Attachment[BUFFER_AUX0];
commit 7df1b901b92407fcfc96543ca7db5604cfa4051d
Author: Tapani Pälli <tapani.palli@intel.com>
Date: Fri Oct 27 12:54:02 2017 +0300
i965: unref push_const_bo in intelDestroyContext
Valgrind shows that leak is caused by gen6_upload_push_constant, add
unref push_const_bo per stage to destructor to fix this (like done for
scratch_bo).
==10952== 144 bytes in 1 blocks are definitely lost in loss record 44 of 66
==10952== at 0x4C30A1E: calloc (vg_replace_malloc.c:711)
==10952== by 0x8C02847: bo_alloc_internal.constprop.10 (brw_bufmgr.c:344)
==10952== by 0x8C425C4: intel_upload_space (intel_upload.c:101)
==10952== by 0x8C22ED0: gen6_upload_push_constants (gen6_constant_state.c:154)
v2: remove if conditions, brw_bo_unreference handles NULL (Ken, Emil)
Fixes: 24891d7c05 ("i965: Store per-stage push constant BO pointers.")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 0b131ca427d788ae08426bdeddb8f4bd3c7da202)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index c8de074..f0adaca 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1072,6 +1072,12 @@ intelDestroyContext(__DRIcontext * driContextPriv)
if (brw->wm.base.scratch_bo)
brw_bo_unreference(brw->wm.base.scratch_bo);
+ brw_bo_unreference(brw->vs.base.push_const_bo);
+ brw_bo_unreference(brw->tcs.base.push_const_bo);
+ brw_bo_unreference(brw->tes.base.push_const_bo);
+ brw_bo_unreference(brw->gs.base.push_const_bo);
+ brw_bo_unreference(brw->wm.base.push_const_bo);
+
brw_destroy_hw_context(brw->bufmgr, brw->hw_ctx);
if (ctx->swrast_context) {
commit cbb8aec81cf55d4ebafbfb60f4a3538d2f10fbef
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Mon Oct 23 14:25:44 2017 -0700
i965/miptree: Take an isl_format in render_aux_usage
Not all rendering matches the miptree format. We allow rendering to
texture views so there are cases where it may not match. In those
cases, our current scheme of just passing the value of ctx->sRGBEnabled
isn't viable. Instead, just do what we do for texturing and pass the
view format in directly.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 39c5c12f8fbee9eec26a627f247d1f3ef7d4bf39)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 05204a9..58e1f8a 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -332,7 +332,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
enum isl_format dst_isl_format =
brw_blorp_to_isl_format(brw, dst_format, true);
enum isl_aux_usage dst_aux_usage =
- intel_miptree_render_aux_usage(brw, dst_mt, encode_srgb, false);
+ intel_miptree_render_aux_usage(brw, dst_mt, dst_isl_format, false);
const bool dst_clear_supported = dst_aux_usage != ISL_AUX_USAGE_NONE;
intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
dst_aux_usage, dst_clear_supported);
@@ -1277,9 +1277,9 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
irb->mt, irb->mt_level, irb->mt_layer, num_layers);
enum isl_aux_usage aux_usage =
- intel_miptree_render_aux_usage(brw, irb->mt, encode_srgb, false);
+ intel_miptree_render_aux_usage(brw, irb->mt, isl_format, false);
intel_miptree_prepare_render(brw, irb->mt, level, irb->mt_layer,
- num_layers, encode_srgb, false);
+ num_layers, isl_format, false);
struct isl_surf isl_tmp[2];
struct blorp_surf surf;
@@ -1298,7 +1298,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
blorp_batch_finish(&batch);
intel_miptree_finish_render(brw, irb->mt, level, irb->mt_layer,
- num_layers, encode_srgb, false);
+ num_layers, isl_format, false);
}
return;
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index b74ab8b..1e5c499 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -25,6 +25,7 @@
#include <sys/errno.h>
+#include "main/blend.h"
#include "main/context.h"
#include "main/condrender.h"
#include "main/samplerobj.h"
@@ -503,9 +504,13 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw)
if (irb == NULL || irb->mt == NULL)
continue;
+ mesa_format mesa_format =
+ _mesa_get_render_format(ctx, intel_rb_format(irb));
+ enum isl_format isl_format = brw_isl_format_for_mesa_format(mesa_format);
+
intel_miptree_prepare_render(brw, irb->mt, irb->mt_level,
irb->mt_layer, irb->layer_count,
- ctx->Color.sRGBEnabled,
+ isl_format,
ctx->Color.BlendEnabled & (1 << i));
}
}
@@ -571,10 +576,14 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
if (!irb)
continue;
+ mesa_format mesa_format =
+ _mesa_get_render_format(ctx, intel_rb_format(irb));
+ enum isl_format isl_format = brw_isl_format_for_mesa_format(mesa_format);
+
brw_render_cache_set_add_bo(brw, irb->mt->bo);
intel_miptree_finish_render(brw, irb->mt, irb->mt_level,
irb->mt_layer, irb->layer_count,
- ctx->Color.sRGBEnabled,
+ isl_format,
ctx->Color.BlendEnabled & (1 << i));
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index f4e9cf4..d668cd8 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -213,11 +213,6 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_mipmap_tree *mt = irb->mt;
- enum isl_aux_usage aux_usage =
- brw->draw_aux_buffer_disabled[unit] ? ISL_AUX_USAGE_NONE :
- intel_miptree_render_aux_usage(brw, mt, ctx->Color.sRGBEnabled,
- ctx->Color.BlendEnabled & (1 << unit));
-
assert(brw_render_target_supported(brw, rb));
mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
@@ -225,9 +220,15 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
_mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
__func__, _mesa_get_format_name(rb_format));
}
+ enum isl_format isl_format = brw->mesa_to_isl_render_format[rb_format];
+
+ enum isl_aux_usage aux_usage =
+ brw->draw_aux_buffer_disabled[unit] ? ISL_AUX_USAGE_NONE :
+ intel_miptree_render_aux_usage(brw, mt, isl_format,
+ ctx->Color.BlendEnabled & (1 << unit));
struct isl_view view = {
- .format = brw->mesa_to_isl_render_format[rb_format],
+ .format = isl_format,
.base_level = irb->mt_level - irb->mt->first_level,
.levels = 1,
.base_array_layer = irb->mt_layer,
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 56105ef..78c29bc 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2654,7 +2654,8 @@ intel_miptree_prepare_image(struct brw_context *brw,
enum isl_aux_usage
intel_miptree_render_aux_usage(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- bool srgb_enabled, bool blend_enabled)
+ enum isl_format render_format,
+ bool blend_enabled)
{
switch (mt->aux_usage) {
case ISL_AUX_USAGE_MCS:
@@ -2665,12 +2666,8 @@ intel_miptree_render_aux_usage(struct brw_context *brw,
return mt->mcs_buf ? ISL_AUX_USAGE_CCS_D : ISL_AUX_USAGE_NONE;
case ISL_AUX_USAGE_CCS_E: {
- mesa_format mesa_format =
- srgb_enabled ? mt->format :_mesa_get_srgb_format_linear(mt->format);
- enum isl_format isl_format = brw_isl_format_for_mesa_format(mesa_format);
-
/* If the format supports CCS_E, then we can just use it */
- if (isl_format_supports_ccs_e(&brw->screen->devinfo, isl_format))
+ if (isl_format_supports_ccs_e(&brw->screen->devinfo, render_format))
return ISL_AUX_USAGE_CCS_E;
/* Otherwise, we have to fall back to CCS_D */
@@ -2679,8 +2676,8 @@ intel_miptree_render_aux_usage(struct brw_context *brw,
* formats. However, there are issues with blending where it doesn't
* properly apply the sRGB curve to the clear color when blending.
*/
- if (blend_enabled && isl_format_is_srgb(isl_format) &&
- !isl_color_value_is_zero_one(mt->fast_clear_color, isl_format))
+ if (blend_enabled && isl_format_is_srgb(render_format) &&
+ !isl_color_value_is_zero_one(mt->fast_clear_color, render_format))
return ISL_AUX_USAGE_NONE;
return ISL_AUX_USAGE_CCS_D;
@@ -2695,10 +2692,11 @@ void
intel_miptree_prepare_render(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t level,
uint32_t start_layer, uint32_t layer_count,
- bool srgb_enabled, bool blend_enabled)
+ enum isl_format render_format,
+ bool blend_enabled)
{
enum isl_aux_usage aux_usage =
- intel_miptree_render_aux_usage(brw, mt, srgb_enabled, blend_enabled);
+ intel_miptree_render_aux_usage(brw, mt, render_format, blend_enabled);
intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
aux_usage, aux_usage != ISL_AUX_USAGE_NONE);
}
@@ -2707,12 +2705,13 @@ void
intel_miptree_finish_render(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t level,
uint32_t start_layer, uint32_t layer_count,
- bool srgb_enabled, bool blend_enabled)
+ enum isl_format render_format,
+ bool blend_enabled)
{
assert(_mesa_is_format_color_format(mt->format));
enum isl_aux_usage aux_usage =
- intel_miptree_render_aux_usage(brw, mt, srgb_enabled, blend_enabled);
+ intel_miptree_render_aux_usage(brw, mt, render_format, blend_enabled);
intel_miptree_finish_write(brw, mt, level, start_layer, layer_count,
aux_usage);
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index c24b5a3..5b7d7ef 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -650,17 +650,20 @@ intel_miptree_prepare_image(struct brw_context *brw,
enum isl_aux_usage
intel_miptree_render_aux_usage(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- bool srgb_enabled, bool blend_enabled);
+ enum isl_format render_format,
+ bool blend_enabled);
void
intel_miptree_prepare_render(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t level,
uint32_t start_layer, uint32_t layer_count,
- bool srgb_enabled, bool blend_enabled);
+ enum isl_format render_format,
+ bool blend_enabled);
void
intel_miptree_finish_render(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t level,
uint32_t start_layer, uint32_t layer_count,
- bool srgb_enabled, bool blend_enabled);
+ enum isl_format render_format,
+ bool blend_enabled);
void
intel_miptree_prepare_depth(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t level,
commit ff8c152640e9ca657db3c02fed07af5c22af303b
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Mon Oct 23 14:24:06 2017 -0700
i965/blorp: Use more temporary isl_format variables
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 78e50185d6f9546f8b09cf281f5e5a17195a7ee5)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index f7d128d..05204a9 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -329,6 +329,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
intel_miptree_prepare_access(brw, src_mt, src_level, 1, src_layer, 1,
src_aux_usage, src_clear_supported);
+ enum isl_format dst_isl_format =
+ brw_blorp_to_isl_format(brw, dst_format, true);
enum isl_aux_usage dst_aux_usage =
intel_miptree_render_aux_usage(brw, dst_mt, encode_srgb, false);
const bool dst_clear_supported = dst_aux_usage != ISL_AUX_USAGE_NONE;
@@ -352,10 +354,9 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_blit(&batch, &src_surf, src_level, src_layer,
- brw_blorp_to_isl_format(brw, src_format, false), src_isl_swizzle,
+ src_isl_format, src_isl_swizzle,
&dst_surf, dst_level, dst_layer,
- brw_blorp_to_isl_format(brw, dst_format, true),
- ISL_SWIZZLE_IDENTITY,
+ dst_isl_format, ISL_SWIZZLE_IDENTITY,
src_x0, src_y0, src_x1, src_y1,
dst_x0, dst_y0, dst_x1, dst_y1,
filter, mirror_x, mirror_y);
@@ -1158,6 +1159,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
mesa_format format = irb->Base.Base.Format;
if (!encode_srgb && _mesa_get_format_color_encoding(format) == GL_SRGB)
format = _mesa_get_srgb_format_linear(format);
+ enum isl_format isl_format = brw->mesa_to_isl_render_format[format];
x0 = fb->_Xmin;
x1 = fb->_Xmax;
@@ -1256,8 +1258,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw, 0);
- blorp_fast_clear(&batch, &surf,
- brw->mesa_to_isl_render_format[format],
+ blorp_fast_clear(&batch, &surf, isl_format,
level, irb->mt_layer, num_layers,
x0, y0, x1, y1);
blorp_batch_finish(&batch);
@@ -1290,9 +1291,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw, 0);
- blorp_clear(&batch, &surf,
- brw->mesa_to_isl_render_format[format],
- ISL_SWIZZLE_IDENTITY,
+ blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
level, irb->mt_layer, num_layers,
x0, y0, x1, y1,
clear_color, color_write_disable);
commit 0fef0c7deb271452f63fad2f77fd256289c2c01a
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Mon Oct 23 15:51:21 2017 -0700
i965/blorp: Use blorp_to_isl_format for src_isl_format in blit_miptrees
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 94389943b63bf8e25fecbbdf357ae5da100d2fc9)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index ed4f987..f7d128d 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
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