mesa: Changes to 'upstream-experimental'
Rebased ref, commits from common ancestor:
commit ae720e28735453f97db23a7345ed109b0b40b300
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Oct 23 13:30:56 2017 +0100
Update version to 17.3.0-rc1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/VERSION b/VERSION
index 12c2e3a..dd84678 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.3.0-devel
+17.3.0-rc1
commit 2665d012a8a12971c87861e789a520951df42f3c
Author: Juan A. Suarez Romero <jasuarez@igalia.com>
Date: Thu Oct 19 12:46:02 2017 +0200
radv: automake: include radv_extensions.py in the tarball
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index 7364e54..6b352ae 100644
--- a/src/amd/vulkan/Makefile.am
+++ b/src/amd/vulkan/Makefile.am
@@ -132,6 +132,7 @@ EXTRA_DIST = \
dev_icd.json.in \
radeon_icd.json.in \
radv_entrypoints_gen.py \
+ radv_extensions.py \
vk_format_layout.csv \
vk_format_parse.py \
vk_format_table.py
commit a548b727a147b4ead1accef10499c4cf81af3057
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Mon Oct 23 03:27:28 2017 +0200
ac/nir: Only clamp shadow reference on radeonsi.
Vulkan CTS does not expect the value to be clamped (at least for D32),
and it makes a differences even though depth is in [0,1], due
to strict inequalities.
I couldn't find anything in the Vulkan spec about this, but the test
seemed to be copied from GL tests and the GL spec only specifies
clamping for fixed point formats. Hence I expect radeonsi to run into
this at some point as well, but given that they still have a usecase
with the Z16->Z32 promotion, I'll leave that for someone else to clean
up.
This at least fixes radv dEQP-VK.texture.shadow.* on VI.
Fixes: 0f9e32519bb 'ac/nir: clamp shadow texture comparison value on VI'
Reviewed-by: Dave Airlie <airlied@redhat.com>
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 5e5a46a..2ddc748 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4652,14 +4652,14 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
LLVMValueRef z = ac_to_float(&ctx->ac,
llvm_extract_elem(&ctx->ac, comparator, 0));
- /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
+ /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
* so the depth comparison value isn't clamped for Z16 and
* Z24 anymore. Do it manually here.
*
* It's unnecessary if the original texture format was
* Z32_FLOAT, but we don't know that here.
*/
- if (ctx->ac.chip_class == VI)
+ if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
z = ac_build_clamp(&ctx->ac, z);
address[count++] = z;
@@ -6600,6 +6600,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ctx.abi.emit_outputs = handle_shader_outputs_post;
ctx.abi.load_ssbo = radv_load_ssbo;
ctx.abi.load_sampler_desc = radv_get_sampler_desc;
+ ctx.abi.clamp_shadow_reference = false;
if (shader_count >= 2)
ac_init_exec_full_mask(&ctx.ac);
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 9579aee..1d9ec8c 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -80,6 +80,7 @@ struct ac_nir_compiler_options {
struct ac_shader_variant_key key;
bool unsafe_math;
bool supports_spill;
+ bool clamp_shadow_reference;
enum radeon_family family;
enum chip_class chip_class;
};
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index 5f296be..14517d5 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -88,6 +88,10 @@ struct ac_shader_abi {
LLVMValueRef index,
enum ac_descriptor_type desc_type,
bool image, bool write);
+
+ /* Whether to clamp the shadow reference value to [0,1]on VI. Radeonsi currently
+ * uses it due to promoting D16 to D32, but radv needs it off. */
+ bool clamp_shadow_reference;
};
#endif /* AC_SHADER_ABI_H */
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c
index a2d1753..e186661 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -498,6 +498,7 @@ bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
ctx->abi.inputs = &ctx->inputs[0];
ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
+ ctx->abi.clamp_shadow_reference = true;
ctx->num_samplers = util_last_bit(info->samplers_declared);
ctx->num_images = util_last_bit(info->images_declared);
commit c07d719e8b683e1bf78f187dd17fe4716f4e5e9c
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sun Oct 22 18:43:14 2017 +0200
radv: Disallow indirect outputs for GS on GFX9 as well.
Since it also uses the output vector before writing to memory.
Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 07e68d6..6176a2e 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -265,9 +265,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
indirect_mask |= nir_var_shader_in;
}
if (!llvm_has_working_vgpr_indexing &&
- (nir->info.stage == MESA_SHADER_VERTEX ||
- nir->info.stage == MESA_SHADER_TESS_EVAL ||
- nir->info.stage == MESA_SHADER_FRAGMENT))
+ nir->info.stage != MESA_SHADER_TESS_CTRL)
indirect_mask |= nir_var_shader_out;
/* TODO: We shouldn't need to do this, however LLVM isn't currently
commit 2c5b43c87fc4e5dcc50f72d782d7b3718e3c2c1c
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sun Oct 22 18:32:14 2017 +0200
ac/nir: Fix nir_texop_lod on GFX for 1D arrays.
Fixes: 1bcb953e166 'radv: handle GFX9 1D textures'
Reviewed-by: Dave Airlie <airlied@redhat.com>
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 360ca81..5e5a46a 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4747,7 +4747,9 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
filler = LLVMConstReal(ctx->ac.f32, 0.5);
if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
- if (instr->is_array) {
+ /* No nir_texop_lod, because it does not take a slice
+ * even with array textures. */
+ if (instr->is_array && instr->op != nir_texop_lod ) {
address[count] = address[count - 1];
address[count - 1] = filler;
count++;
commit da9c3cd3ee5494b43a8ab3f9a3fee95620d9d357
Author: Dave Airlie <airlied@redhat.com>
Date: Mon Oct 23 06:23:29 2017 +1000
radv/ac/nir: only emit tess factors to storage if tes reads them
Otherwise we just need to write them to the tf ring.
this seems to improve the tessellation demo on Bonarie
~2190->~2230 fps
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 83b49b5..360ca81 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6166,8 +6166,8 @@ write_tess_factors(struct nir_to_llvm_context *ctx)
stride - 4, byteoffset, tf_base,
16 + tf_offset, 1, 0, true, false);
- //TODO store to offchip for TES to read - only if TES reads them
- if (1) {
+ //store to offchip for TES to read - only if TES reads them
+ if (ctx->options->key.tcs.tes_reads_tess_factors) {
LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
LLVMValueRef tf_inner_offset;
unsigned param_outer, param_inner;
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index eecc2cb..9579aee 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -55,6 +55,7 @@ struct ac_tcs_variant_key {
struct ac_vs_variant_key vs_key;
unsigned primitive_mode;
unsigned input_vertices;
+ uint32_t tes_reads_tess_factors:1;
};
struct ac_fs_variant_key {
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f23afa4..669d9a4 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1773,6 +1773,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
if (keys)
keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
+ keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
}
commit 6ce550453f1df64caeb956f215d32da96b89f2b1
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sun Oct 22 00:56:09 2017 +0200
radv: Don't use vgpr indexing for outputs on GFX9.
Due to LLVM bugs. Fixes a bunch of dEQP-VK.glsl.indexing.*
tests.
Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Dave Airlie <airlied@redhat.com>
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index e572f69..07e68d6 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -264,6 +264,11 @@ radv_shader_compile_to_nir(struct radv_device *device,
!llvm_has_working_vgpr_indexing)) {
indirect_mask |= nir_var_shader_in;
}
+ if (!llvm_has_working_vgpr_indexing &&
+ (nir->info.stage == MESA_SHADER_VERTEX ||
+ nir->info.stage == MESA_SHADER_TESS_EVAL ||
+ nir->info.stage == MESA_SHADER_FRAGMENT))
+ indirect_mask |= nir_var_shader_out;
/* TODO: We shouldn't need to do this, however LLVM isn't currently
* smart enough to handle indirects without causing excess spilling
commit ad727b96b650a8223f9853f1cde8353f4bf83c06
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sat Oct 21 22:00:37 2017 +0200
ac/nir: Account for compact array index in GS input load from LDS.
Mirrors the vram path.
Fixes: d4ecc3c9299 'ac/nir: Add loading from LDS for merged GS.'
Reviewed-by: Dave Airlie <airlied@redhat.com>
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index ca856bb..83b49b5 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3011,7 +3011,7 @@ load_gs_input(struct nir_to_llvm_context *ctx,
if (ctx->ac.chip_class >= GFX9) {
LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
- LLVMConstInt(ctx->ac.i32, param * 4 + i, 0), "");
+ LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
value[i] = lds_load(ctx, dw_addr);
} else {
args[0] = ctx->esgs_ring;
commit 67648c0faa262a12f7497ffda44f048f42e816a0
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sat Oct 21 21:14:13 2017 +0200
radv: Don't compile shaders when they are cached already.
When the gs_copy_shader is NULL (due to an incomplete cache), but
the main shaders are found, we still do the nir, but we shouldn't
compile the shaders again. For merged shaders we should also account
for the missing shaders.
Fixes: ce03c119ce0 'radv: Add code to compile merged shaders.'
Reviewed-by: Dave Airlie <airlied@redhat.com>
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index db55081..f23afa4 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1779,10 +1779,12 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
radv_link_shaders(pipeline, nir);
if (nir[MESA_SHADER_FRAGMENT]) {
- pipeline->shaders[MESA_SHADER_FRAGMENT] =
- radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
- pipeline->layout, keys ? keys + MESA_SHADER_FRAGMENT : 0,
- &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
+ if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
+ pipeline->shaders[MESA_SHADER_FRAGMENT] =
+ radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
+ pipeline->layout, keys ? keys + MESA_SHADER_FRAGMENT : 0,
+ &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
+ }
/* TODO: These are no longer used as keys we should refactor this */
if (keys) {
@@ -1793,26 +1795,28 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
}
}
- if (device->physical_device->rad_info.chip_class >= GFX9 &&
- modules[MESA_SHADER_TESS_CTRL] && !pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
- struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
- struct ac_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
- key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
- pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
- pipeline->layout,
- &key, &codes[MESA_SHADER_TESS_CTRL],
- &code_sizes[MESA_SHADER_TESS_CTRL]);
+ if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
+ if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
+ struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
+ struct ac_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
+ key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
+ pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
+ pipeline->layout,
+ &key, &codes[MESA_SHADER_TESS_CTRL],
+ &code_sizes[MESA_SHADER_TESS_CTRL]);
+ }
modules[MESA_SHADER_VERTEX] = NULL;
}
- if (device->physical_device->rad_info.chip_class >= GFX9 &&
- modules[MESA_SHADER_GEOMETRY] && !pipeline->shaders[MESA_SHADER_GEOMETRY]) {
+ if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
- struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
- pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
- pipeline->layout,
- &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
+ if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
+ struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
+ pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
+ pipeline->layout,
+ &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
&code_sizes[MESA_SHADER_GEOMETRY]);
+ }
modules[pre_stage] = NULL;
}
commit 3bf954b28ec79340227a366576382c719754dec5
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sat Oct 21 20:16:57 2017 +0200
radv: Don't check for max GL GS invocations.
We specify 127 instead of 32 as the limit in vulkan.
Fixes: 6bc42855f92 'radv: enable GS on GFX9'
Reviewed-by: Dave Airlie <airlied@redhat.com>
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index eac4456..db55081 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1196,8 +1196,6 @@ static void calculate_gfx9_gs_info(const VkGraphicsPipelineCreateInfo *pCreateIn
unsigned max_gs_prims, gs_prims;
unsigned min_es_verts, es_verts, worst_case_es_verts;
- assert(gs_num_invocations <= 32); /* GL maximum */
-
if (uses_adjacency || gs_num_invocations > 1)
max_gs_prims = 127 / gs_num_invocations;
else
commit 050f7e2df2ea4230320952f16e9f9558bcf6d5d3
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sat Oct 21 18:23:47 2017 +0200
radv: Don't explicitly reference vertex shader for draw_id.
With merged shaders the vertex shader may not exist. This got in
because the offending patch was written before merged shaders were
upstream, but committed after.
Fixes: 75dfab24a2c 'radv: refactor indirect draws with radv_draw_info'
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 7ba0ea0..ba382c8 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2954,7 +2954,7 @@ radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
struct radeon_winsys_cs *cs = cmd_buffer->cs;
unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
: V_0287F0_DI_SRC_SEL_AUTO_INDEX;
- bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
+ bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
assert(base_reg);
commit 20fb15bfe4888c8a09e3ace668caeb9e805e350e
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sat Oct 21 18:20:24 2017 +0200
radv: Don't reset cmd_buffer->state.dirty.
Otherwise for non-indexed draws we set and immediately unset
RADV_CMD_DIRTY_INDEX_BUFFER. As all the set functions should
clear their own bit, this is unnecessary.
Fixes: 341529dbee5 'radv: use optimal packet order for draws'
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 887b789..7ba0ea0 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3151,8 +3151,6 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
radv_emit_draw_registers(cmd_buffer, info->indexed,
info->instance_count > 1, info->indirect,
info->indirect ? 0 : info->count);
-
- cmd_buffer->state.dirty = 0;
}
static void
commit fb55477990e417f3a5e80d91e9e0dbb7bf2f71a6
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sat Oct 21 18:16:15 2017 +0200
radv: Correctly detect changed shaders for vertex descriptors.
As they were emitted after the new pipeline, the changed pipeline
detection was not working anymore.
Fixes: 341529dbee5 'radv: use optimal packet order for draws'
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index d511659..887b789 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1719,11 +1719,11 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
}
static bool
-radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
+radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
{
struct radv_device *device = cmd_buffer->device;
- if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
+ if ((pipeline_is_dirty || cmd_buffer->state.vb_dirty) &&
cmd_buffer->state.pipeline->vertex_elements.count &&
radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
@@ -1771,9 +1771,9 @@ radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
}
static bool
-radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
+radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
{
- if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer))
+ if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
return false;
radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
@@ -3186,7 +3186,7 @@ radv_draw(struct radv_cmd_buffer *cmd_buffer,
si_emit_cache_flush(cmd_buffer);
/* <-- CUs are idle here --> */
- if (!radv_upload_graphics_shader_descriptors(cmd_buffer))
+ if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
return;
radv_emit_draw_packets(cmd_buffer, info);
@@ -3211,7 +3211,7 @@ radv_draw(struct radv_cmd_buffer *cmd_buffer,
cmd_buffer->state.pipeline);
}
- if (!radv_upload_graphics_shader_descriptors(cmd_buffer))
+ if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
return;
radv_emit_all_graphics_states(cmd_buffer, info);
commit 24fe4e6143aa06a8aaa1b2cabaee84064a0efbd9
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sat Oct 21 03:07:43 2017 +0200
ac/nir: Set larged wrokgroup size for GS on GFX9.
They don't take a single wave anymore and we need the barriers.
Fixes: 6bc42855f92 'radv: enable GS on GFX9'
Reviewed-by: Dave Airlie <airlied@redhat.com>
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 02420f4..ca856bb 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6457,7 +6457,7 @@ ac_nir_get_max_workgroup_size(enum chip_class chip_class,
case MESA_SHADER_TESS_CTRL:
return chip_class >= CIK ? 128 : 64;
case MESA_SHADER_GEOMETRY:
- return 64;
+ return chip_class >= GFX9 ? 128 : 64;
case MESA_SHADER_COMPUTE:
break;
default:
commit 9e82f2b3ea126d297286e71eab5311afcca16f25
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sat Oct 21 03:04:35 2017 +0200
ac/nir: Take the max workgroup size of all provided shaders.
Fixes: ffaf4d608a1 'radv: Enable tessellation shaders for GFX9.'
Reviewed-by: Dave Airlie <airlied@redhat.com>
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 61ffe91..02420f4 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6584,7 +6584,12 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
for (i = 0; i < AC_UD_MAX_UD; i++)
shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
- ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, shaders[0]);
+ ctx.max_workgroup_size = 0;
+ for (int i = 0; i < shader_count; ++i) {
+ ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
+ ac_nir_get_max_workgroup_size(ctx.options->chip_class,
+ shaders[i]));
+ }
create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
commit 0fdd531457ecaba263e6a27e030d451774f54b32
Author: Alex Smith <asmith@feralinteractive.com>
Date: Thu Oct 19 11:49:39 2017 +0100
radv: Fix pipeline cache locking issues
Need to lock around the whole process of retrieving cached shaders, and
around GetPipelineCacheData.
This fixes GPU hangs observed when creating multiple pipelines in
parallel, which appeared to be due to invalid shader code being pulled
from the cache.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
diff --git a/src/amd/vulkan/radv_pipeline_cache.c b/src/amd/vulkan/radv_pipeline_cache.c
index 034dc35..a75356b 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -177,15 +177,20 @@ radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
struct radv_shader_variant **variants)
{
struct cache_entry *entry;
- if (cache)
- entry = radv_pipeline_cache_search(cache, sha1);
- else
- entry = radv_pipeline_cache_search(device->mem_cache, sha1);
+
+ if (!cache)
+ cache = device->mem_cache;
+
+ pthread_mutex_lock(&cache->mutex);
+
+ entry = radv_pipeline_cache_search_unlocked(cache, sha1);
if (!entry) {
if (!device->physical_device->disk_cache ||
- (device->instance->debug_flags & RADV_DEBUG_NO_CACHE))
+ (device->instance->debug_flags & RADV_DEBUG_NO_CACHE)) {
+ pthread_mutex_unlock(&cache->mutex);
return false;
+ }
uint8_t disk_sha1[20];
disk_cache_compute_key(device->physical_device->disk_cache,
@@ -193,8 +198,10 @@ radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
entry = (struct cache_entry *)
disk_cache_get(device->physical_device->disk_cache,
disk_sha1, NULL);
- if (!entry)
+ if (!entry) {
+ pthread_mutex_unlock(&cache->mutex);
return false;
+ }
}
char *p = entry->code;
@@ -204,8 +211,10 @@ radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
struct cache_entry_variant_info info;
variant = calloc(1, sizeof(struct radv_shader_variant));
- if (!variant)
+ if (!variant) {
+ pthread_mutex_unlock(&cache->mutex);
return false;
+ }
memcpy(&info, p, sizeof(struct cache_entry_variant_info));
p += sizeof(struct cache_entry_variant_info);
@@ -231,6 +240,7 @@ radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
p_atomic_inc(&entry->variants[i]->ref_count);
memcpy(variants, entry->variants, sizeof(entry->variants));
+ pthread_mutex_unlock(&cache->mutex);
return true;
}
@@ -509,12 +519,17 @@ VkResult radv_GetPipelineCacheData(
RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
struct cache_header *header;
VkResult result = VK_SUCCESS;
+
+ pthread_mutex_lock(&cache->mutex);
+
const size_t size = sizeof(*header) + cache->total_size;
if (pData == NULL) {
+ pthread_mutex_unlock(&cache->mutex);
*pDataSize = size;
return VK_SUCCESS;
}
if (*pDataSize < sizeof(*header)) {
+ pthread_mutex_unlock(&cache->mutex);
*pDataSize = 0;
return VK_INCOMPLETE;
}
@@ -545,6 +560,7 @@ VkResult radv_GetPipelineCacheData(
}
*pDataSize = p - pData;
+ pthread_mutex_unlock(&cache->mutex);
return result;
}
commit c71d44c7f845a9ef23251d9a0c95267f4a711578
Author: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Date: Fri Oct 20 18:49:30 2017 +0100
anv: don't assert on device init on Cannonlake
v2: Warn that support is still in alpha (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index a305afe..67028e8 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -300,8 +300,10 @@ anv_physical_device_init(struct anv_physical_device *device,
} else if (device->info.gen == 7 && device->info.is_baytrail) {
intel_logw("Bay Trail Vulkan support is incomplete");
} else if (device->info.gen >= 8 && device->info.gen <= 9) {
- /* Broadwell, Cherryview, Skylake, Broxton, Kabylake is as fully
- * supported as anything */
+ /* Broadwell, Cherryview, Skylake, Broxton, Kabylake, Coffelake is as
+ * fully supported as anything */
+ } else if (device->info.gen == 10) {
+ intel_logw("Cannonlake Vulkan support is alpha");
} else {
result = vk_errorf(device->instance, device,
VK_ERROR_INCOMPATIBLE_DRIVER,
commit 0c95adaf9eb9763016c3319fef6d581b4d6d7359
Author: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Date: Fri Oct 20 18:28:48 2017 +0100
anv: disable stencil pma fix on Gen > 9
This workaround isn't listed on Gen10.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c b/src/intel/vulkan/gen8_cmd_buffer.c
index f19867c..751212b 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -259,6 +259,8 @@ want_depth_pma_fix(struct anv_cmd_buffer *cmd_buffer)
UNUSED static bool
want_stencil_pma_fix(struct anv_cmd_buffer *cmd_buffer)
{
+ if (GEN_GEN > 9)
+ return false;
assert(GEN_GEN == 9);
/* From the Skylake PRM Vol. 2c CACHE_MODE_1::STC PMA Optimization Enable:
commit 0c92651a3bf4471ced629237d9857e8b5e91d84b
Author: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Date: Fri Oct 20 15:46:48 2017 +0100
blorp: enable R32G32B32X32 blorp ccs copies
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 11c2116a..4507046 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -2206,6 +2206,7 @@ get_ccs_compatible_uint_format(const struct isl_format_layout *fmtl)
case ISL_FORMAT_R32G32B32A32_UINT:
case ISL_FORMAT_R32G32B32A32_UNORM:
case ISL_FORMAT_R32G32B32A32_SNORM:
+ case ISL_FORMAT_R32G32B32X32_FLOAT:
return ISL_FORMAT_R32G32B32A32_UINT;
case ISL_FORMAT_R16G16B16A16_UNORM:
commit 48615d1ead9ae039b6b8a6b794d5a63d6514b90e
Author: Eric Anholt <eric@anholt.net>
Date: Fri Oct 20 17:14:52 2017 -0700
meson: Fix vc5 deps on the XML-generated headers.
I typoed and was depending on v3d_xml.h (the gzipped xml)_, not on the
v3d_packet_v33_pack.h that the compiler and QPU packing actually use.
diff --git a/src/broadcom/compiler/meson.build b/src/broadcom/compiler/meson.build
index bedf0ad..3c62819 100644
--- a/src/broadcom/compiler/meson.build
+++ b/src/broadcom/compiler/meson.build
@@ -35,7 +35,7 @@ libbroadcom_compiler_files = files(
)
libbroadcom_compiler = static_library(
- ['broadcom_compiler', v3d_xml_h, nir_opcodes_h, nir_builder_opcodes_h],
+ ['broadcom_compiler', v3d_xml_pack, nir_opcodes_h, nir_builder_opcodes_h],
libbroadcom_compiler_files,
include_directories : [inc_common, inc_broadcom],
c_args : [c_vis_args, no_override_init_args],
diff --git a/src/broadcom/qpu/meson.build b/src/broadcom/qpu/meson.build
index ca90aa2..8178ddb 100644
--- a/src/broadcom/qpu/meson.build
+++ b/src/broadcom/qpu/meson.build
@@ -25,7 +25,7 @@ libbroadcom_qpu_files = files(
)
libbroadcom_qpu = static_library(
- ['broadcom_qpu', v3d_xml_h],
+ ['broadcom_qpu', v3d_xml_pack],
libbroadcom_qpu_files,
include_directories : [inc_common, inc_broadcom],
c_args : [c_vis_args, no_override_init_args],
commit 07bfdb478bf844a0ac9cf3679f51f83c4abea5a1
Author: Eric Anholt <eric@anholt.net>
Date: Fri Oct 20 17:05:54 2017 -0700
broadcom/vc5: Propagate vc4 aliasing fix to vc5.
See e5fea0d621af2b14cf6c5e364eeaf293db460f2a
diff --git a/src/broadcom/compiler/vir_lower_uniforms.c b/src/broadcom/compiler/vir_lower_uniforms.c
index b274199..7f3bb84 100644
--- a/src/broadcom/compiler/vir_lower_uniforms.c
+++ b/src/broadcom/compiler/vir_lower_uniforms.c
@@ -66,7 +66,7 @@ remove_uniform(struct hash_table *ht, struct qreg reg)
entry = _mesa_hash_table_search(ht, key);
assert(entry);
- entry->data--;
+ entry->data = (void *)(((uintptr_t) entry->data) - 1);
if (entry->data == NULL)
_mesa_hash_table_remove(ht, entry);
}
commit e5fea0d621af2b14cf6c5e364eeaf293db460f2a
Author: Stefan Schake <stschake@gmail.com>
Date: Fri Oct 20 16:16:44 2017 +0200
broadcom/vc4: Fix aliasing issue
This was causing Android clang version 3.8.256229 to miscompile,
presumably due to strict aliasing.
Fixes: 14dc281c1332 ("vc4: Enforce one-uniform-per-instruction after optimization.")
diff --git a/src/gallium/drivers/vc4/vc4_qir_lower_uniforms.c b/src/gallium/drivers/vc4/vc4_qir_lower_uniforms.c
index 9ecfe65..ad19f06 100644
--- a/src/gallium/drivers/vc4/vc4_qir_lower_uniforms.c
+++ b/src/gallium/drivers/vc4/vc4_qir_lower_uniforms.c
@@ -66,7 +66,7 @@ remove_uniform(struct hash_table *ht, struct qreg reg)
entry = _mesa_hash_table_search(ht, key);
assert(entry);
- entry->data--;
+ entry->data = (void *)(((uintptr_t) entry->data) - 1);
if (entry->data == NULL)
_mesa_hash_table_remove(ht, entry);
}
commit 035ec7a2bb2d5e413ac945b8f012185a0e187d5e
Author: Dylan Baker <dylan@pnwbakers.com>
Date: Wed Oct 18 15:11:39 2017 -0700
meson: Add support for EGL glvnd
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Tested-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
diff --git a/src/egl/meson.build b/src/egl/meson.build
index ade6810..8ea8a5b 100644
--- a/src/egl/meson.build
+++ b/src/egl/meson.build
@@ -70,6 +70,34 @@ linux_dmabuf_unstable_v1_client_protocol_h = custom_target(
command : [prog_wl_scanner, 'client-header', '@INPUT@', '@OUTPUT@'],
)
+g_egldispatchstubs_c = custom_target(
+ 'g_egldispatchstubs.c',
+ input : [
+ 'generate/gen_egl_dispatch.py', 'generate/eglFunctionList.py',
+ 'generate/egl.xml', 'generate/egl_other.xml'
+ ],
+ output : 'g_egldispatchstubs.c',
+ command : [
+ prog_python2, '@INPUT0@', 'source', '@INPUT1@', '@INPUT2@', '@INPUT3@'
+ ],
+ depend_files : files('generate/genCommon.py'),
+ capture : true,
+)
+
+g_egldispatchstubs_h = custom_target(
+ 'g_egldispatchstubs.h',
+ input : [
+ 'generate/gen_egl_dispatch.py', 'generate/eglFunctionList.py',
+ 'generate/egl.xml', 'generate/egl_other.xml'
+ ],
+ output : 'g_egldispatchstubs.h',
+ command : [
+ prog_python2, '@INPUT0@', 'header', '@INPUT1@', '@INPUT2@', '@INPUT3@'
+ ],
+ depend_files : files('generate/genCommon.py'),
+ capture : true,
+)
+
if with_platform_x11
files_egl += files('drivers/dri2/platform_x11.c')
if with_dri3
@@ -107,8 +135,22 @@ if cc.has_function('mincore')
c_args_for_egl += '-DHAVE_MINCORE'
endif
+if not with_glvnd
+ egl_lib_name = 'EGL'
+ egl_lib_version = '1.0.0'
+else
+ egl_lib_name = 'EGL_mesa'
+ egl_lib_version = '0'
+ files_egl += [g_egldispatchstubs_h, g_egldispatchstubs_c]
+ files_egl += files('main/eglglvnd.c', 'main/egldispatchstubs.c')
+ install_data(
+ 'main/50_mesa.json',
+ install_dir : join_paths(get_option('datadir'), 'glvnd', 'egl_vendor.d')
+ )
+endif
+
libegl = shared_library(
- 'EGL',
+ egl_lib_name,
files_egl,
c_args : [
c_vis_args,
@@ -125,7 +167,7 @@ libegl = shared_library(
link_args : [ld_args_bsymbolic, ld_args_gc_sections],
dependencies : [deps_for_egl, dep_dl, dep_libdrm, dep_clock, dep_thread],
install : true,
- version : '1.0.0',
+ version : egl_lib_version,
)
pkg.generate(
commit 108d257a16859898f5ce02f4759c5c58f9b8c050
Author: Dylan Baker <dylan@pnwbakers.com>
Date: Wed Oct 18 12:20:43 2017 -0700
meson: build libEGL
This is based heavily on Daniel Stone's work for the same, rebased on
master and with a number of TODO's fixed.
This does not implement glvnd (which is coming in a later patch)
Meson builds egl slightly differently than autotools, namely it doesn't
build an intermediate shared library. It doesn't do this because meson
doesn't have problems with the name of the library being dynamically
generated, so the glvnd and non-glvnd code can follow the same path.
v2: - Don't reuse variable (Eric E.)
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Tested-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
diff --git a/include/meson.build b/include/meson.build
index e33a856..88e66a1 100644
--- a/include/meson.build
+++ b/include/meson.build
@@ -58,3 +58,11 @@ endif
if with_osmesa
install_headers('GL/osmesa.h', subdir : 'GL')
endif
+
+if with_egl
+ install_headers(
+ 'EGL/eglext.h', 'EGL/egl.h', 'EGL/eglextchromium.h', 'EGL/eglmesaext.h',
+ 'EGL/eglplatform.h',
+ subdir : 'EGL',
+ )
+endif
diff --git a/meson.build b/meson.build
index a8bcaf7..92b875b 100644
--- a/meson.build
+++ b/meson.build
@@ -130,16 +130,20 @@ endif
# TODO: other OSes
with_dri_platform = 'drm'
-# TODO: there are more platforms required for non-vulkan drivers
+# TODO: android platform
with_platform_wayland = false
with_platform_x11 = false
with_platform_drm = false
+with_platform_surfaceless = false
+egl_native_platform = ''
_platforms = get_option('platforms')
if _platforms != ''
_split = _platforms.split(',')
with_platform_x11 = _split.contains('x11')
with_platform_wayland = _split.contains('wayland')
with_platform_drm = _split.contains('drm')
+ with_platform_surfaceless = _split.contains('surfaceless')
+ egl_native_platform = _split[0]
endif
with_gbm = get_option('gbm')
@@ -154,6 +158,27 @@ else
with_gbm = false
endif
+_egl = get_option('egl')
+if _egl == 'auto'
+ with_egl = with_dri and with_shared_glapi and egl_native_platform != ''
+elif _egl == 'yes'
+ if not with_dri
+ error('EGL requires dri')
+ elif not with_shared_glapi
+ error('EGL requires shared-glapi')
+ elif egl_native_platform == ''
+ error('No platforms specified, consider -Dplatforms=drm,x11 at least')
+ endif
+ with_egl = true
+else
+ with_egl = false
+endif
+
+# TODO: or virgl
+if with_egl and with_gallium_radeonsi and not (with_platform_drm or with_platform_surfaceless)
+ error('RadeonSI requires drm or surfaceless platform when using EGL')
+endif
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