mesa: Changes to 'debian-experimental'
Makefile.am | 2
VERSION | 2
bin/.cherry-ignore | 2
configure.ac | 3
debian/changelog | 2
debian/rules | 7
include/GL/glcorearb.h | 108 +++--
include/GL/glext.h | 87 +++-
src/Makefile.am | 2
src/compiler/Makefile.sources | 2
src/compiler/glsl/ast.h | 3
src/compiler/glsl/ast_function.cpp | 4
src/compiler/glsl/ast_to_hir.cpp | 16
src/compiler/glsl/ast_type.cpp | 17
src/compiler/glsl/glsl_parser_extras.cpp | 2
src/compiler/glsl/link_varyings.cpp | 23 -
src/compiler/nir/nir_lower_indirect_derefs.c | 2
src/compiler/spirv/spirv_info.c | 150 +++++++
src/compiler/spirv/spirv_info.h | 27 +
src/compiler/spirv/spirv_to_nir.c | 123 +++++
src/compiler/spirv/vtn_private.h | 3
src/compiler/spirv/vtn_variables.c | 16
src/gallium/auxiliary/Makefile.am | 7
src/gallium/auxiliary/Makefile.sources | 4
src/gallium/auxiliary/tgsi/tgsi_scan.c | 30 +
src/gallium/auxiliary/tgsi/tgsi_scan.h | 1
src/gallium/auxiliary/util/u_blit.c | 8
src/gallium/auxiliary/vl/vl_winsys_dri3.c | 11
src/gallium/drivers/nouveau/codegen/nv50_ir.cpp | 1
src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 7
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 22 -
src/gallium/drivers/nouveau/codegen/nv50_ir_target.h | 5
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp | 2
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 4
src/gallium/drivers/nouveau/nv50/nv50_formats.c | 2
src/gallium/drivers/nouveau/nvc0/nvc0_compute.c | 7
src/gallium/drivers/nouveau/nvc0/nvc0_context.c | 25 -
src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 1
src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 71 ++-
src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c | 3
src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 31 +
src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 8
src/gallium/drivers/r600/r600_hw_context.c | 19
src/gallium/drivers/radeon/r600_texture.c | 5
src/gallium/drivers/radeon/radeon_winsys.h | 1
src/gallium/drivers/radeonsi/si_descriptors.c | 40 +
src/gallium/drivers/radeonsi/si_hw_context.c | 3
src/gallium/drivers/radeonsi/si_state.h | 1
src/gallium/drivers/swr/Makefile.am | 1
src/gallium/drivers/swr/Makefile.sources | 10
src/gallium/state_trackers/clover/Makefile.am | 1
src/gallium/state_trackers/clover/api/device.cpp | 4
src/gallium/state_trackers/clover/api/platform.cpp | 4
src/gallium/state_trackers/osmesa/osmesa.c | 1
src/gallium/targets/va/Makefile.am | 14
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 1
src/gallium/winsys/virgl/drm/virgl_drm_winsys.c | 2
src/gallium/winsys/virgl/vtest/virgl_vtest_winsys.c | 2
src/glx/glxcmds.c | 23 +
src/intel/genxml/gen6.xml | 4
src/intel/genxml/gen7.xml | 4
src/intel/genxml/gen75.xml | 4
src/intel/isl/Android.mk | 6
src/intel/isl/Makefile.am | 12
src/intel/isl/gen_format_layout.py | 207 ++++++++++
src/intel/isl/isl_format_layout_gen.bash | 129 ------
src/intel/vulkan/Makefile.am | 2
src/intel/vulkan/anv_cmd_buffer.c | 11
src/intel/vulkan/anv_descriptor_set.c | 19
src/intel/vulkan/anv_device.c | 2
src/intel/vulkan/anv_entrypoints_gen.py | 48 +-
src/intel/vulkan/anv_meta_blit.c | 3
src/intel/vulkan/anv_meta_clear.c | 6
src/intel/vulkan/anv_meta_copy.c | 34 -
src/intel/vulkan/anv_nir_apply_pipeline_layout.c | 7
src/intel/vulkan/anv_pipeline.c | 104 +++--
src/intel/vulkan/anv_pipeline_cache.c | 5
src/intel/vulkan/anv_private.h | 16
src/intel/vulkan/gen7_cmd_buffer.c | 12
src/intel/vulkan/gen7_pipeline.c | 49 --
src/intel/vulkan/gen8_cmd_buffer.c | 10
src/intel/vulkan/gen8_pipeline.c | 67 ---
src/intel/vulkan/genX_pipeline_util.h | 87 ++++
src/mapi/glapi/gen/ARB_direct_state_access.xml | 1
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 17
src/mesa/drivers/dri/i965/brw_compiler.h | 34 +
src/mesa/drivers/dri/i965/brw_context.c | 19
src/mesa/drivers/dri/i965/brw_context.h | 25 +
src/mesa/drivers/dri/i965/brw_cs.c | 27 +
src/mesa/drivers/dri/i965/brw_eu_emit.c | 6
src/mesa/drivers/dri/i965/brw_fs.cpp | 132 +++++-
src/mesa/drivers/dri/i965/brw_fs_builder.h | 10
src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 5
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 4
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 108 ++++-
src/mesa/drivers/dri/i965/brw_gs.c | 8
src/mesa/drivers/dri/i965/brw_program.c | 22 +
src/mesa/drivers/dri/i965/brw_tcs.c | 8
src/mesa/drivers/dri/i965/brw_tes.c | 8
src/mesa/drivers/dri/i965/brw_vec4_cmod_propagation.cpp | 12
src/mesa/drivers/dri/i965/brw_vs.c | 8
src/mesa/drivers/dri/i965/brw_vs_state.c | 2
src/mesa/drivers/dri/i965/brw_wm.c | 7
src/mesa/drivers/dri/i965/brw_wm_state.c | 2
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 9
src/mesa/drivers/dri/i965/gen6_gs_state.c | 2
src/mesa/drivers/dri/i965/gen6_vs_state.c | 2
src/mesa/drivers/dri/i965/gen6_wm_state.c | 2
src/mesa/drivers/dri/i965/gen7_blorp.c | 5
src/mesa/drivers/dri/i965/gen7_cs_state.c | 38 +
src/mesa/drivers/dri/i965/gen7_ds_state.c | 2
src/mesa/drivers/dri/i965/gen7_gs_state.c | 2
src/mesa/drivers/dri/i965/gen7_hs_state.c | 2
src/mesa/drivers/dri/i965/gen7_urb.c | 2
src/mesa/drivers/dri/i965/gen7_vs_state.c | 2
src/mesa/drivers/dri/i965/gen7_wm_state.c | 2
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 9
src/mesa/drivers/dri/i965/gen8_ds_state.c | 10
src/mesa/drivers/dri/i965/gen8_gs_state.c | 2
src/mesa/drivers/dri/i965/gen8_hs_state.c | 2
src/mesa/drivers/dri/i965/gen8_ps_state.c | 2
src/mesa/drivers/dri/i965/gen8_vs_state.c | 2
src/mesa/drivers/dri/i965/intel_fbo.c | 2
src/mesa/drivers/dri/i965/intel_screen.c | 5
src/mesa/main/blit.c | 8
src/mesa/main/clear.c | 4
src/mesa/main/clear.h | 2
src/mesa/main/copyimage.c | 13
src/mesa/main/extensions_table.h | 4
src/mesa/main/get_hash_params.py | 2
src/mesa/main/shader_query.cpp | 19
src/mesa/state_tracker/st_atom_image.c | 12
src/mesa/state_tracker/st_cb_bufferobjects.c | 15
src/mesa/state_tracker/st_cb_eglimage.c | 3
src/mesa/state_tracker/st_cb_texture.c | 119 +++--
src/mesa/state_tracker/st_manager.c | 3
src/mesa/state_tracker/st_texture.h | 6
src/mesa/state_tracker/st_vdpau.c | 3
139 files changed, 1925 insertions(+), 691 deletions(-)
New commits:
commit 1741b36aaf3a203bd81a091eaca7d02fd6c4c146
Author: Timo Aaltonen <tjaalton@debian.org>
Date: Mon Jun 20 12:27:20 2016 +0300
rules: partly revert cleanup of clean target, and purge nir/*.pyc
diff --git a/debian/rules b/debian/rules
index 75e4d0e..ce5c53f 100755
--- a/debian/rules
+++ b/debian/rules
@@ -129,7 +129,14 @@ confflags += \
override_dh_clean:
rm -rf .pc
rm -rf build
+ rm -rf configure bin/config.guess bin/config.sub config.h.in
+ rm -rf $$(find -name Makefile.in)
+ rm -rf bin/install-sh bin/ltmain.sh
for file in debian/*.in; do rm -f $${file%%.in}; done
+ rm -f src/compiler/nir/*.pyc
+ rm -f src/mapi/glapi/gen/*.pyc
+ rm -f src/mesa/main/*.pyc
+ rm -f src/gallium/auxiliary/util/*.pyc
dh_clean
commit 11fe5aeb486712b87f0d1b38ee10bf4e252f41a6
Author: Timo Aaltonen <tjaalton@debian.org>
Date: Mon Jun 20 12:14:22 2016 +0300
update changelog
diff --git a/debian/changelog b/debian/changelog
index 50c97cc..b5ce92a 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-mesa (12.0.0~rc2-1) UNRELEASED; urgency=medium
+mesa (12.0.0~rc3-1) UNRELEASED; urgency=medium
* New upstream release candidate.
* symbols: Updated.
commit 7d41c8aa25ce5f695233de18c0586b630cbfdc74
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Wed Jun 15 09:21:11 2016 +0100
Update version to 12.0.0-rc3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/VERSION b/VERSION
index 76ea38e..6ef7d92 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-12.0.0-rc2
+12.0.0-rc3
commit 575f9eaa2d0c8de0bc701b8e928dbf132013388c
Author: Nicolai Hähnle <nicolai.haehnle@amd.com>
Date: Tue Jun 14 18:00:13 2016 +0200
radeonsi: mark buffer texture range valid for shader images
When a shader image view into a buffer texture can be written to, the buffer's
valid range must be updated, or subsequent transfers may incorrectly skip
synchronization.
This fixes a bug that was exposed in Xephyr by PBO acceleration for glReadPixels,
reported by Michel Dänzer.
Cc: Michel Dänzer <michel.daenzer@amd.com>
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit a64c7cd2bac33a3a2bf908b5ef538dff03b93b73)
Back-ported from commit a64c7cd2bac33a3a2bf908b5ef538dff03b93b73:
- include util/u_format.h
- code was extracted to si_set_shader_image in master, move it back
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
--
src/gallium/drivers/radeonsi/si_descriptors.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 57d2ae6..bbd02e9 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -60,6 +60,7 @@
#include "si_shader.h"
#include "sid.h"
+#include "util/u_format.h"
#include "util/u_math.h"
#include "util/u_memory.h"
#include "util/u_suballoc.h"
@@ -482,6 +483,23 @@ si_disable_shader_image(struct si_images_info *images, unsigned slot)
}
static void
+si_mark_image_range_valid(struct pipe_image_view *view)
+{
+ struct r600_resource *res = (struct r600_resource *)view->resource;
+ const struct util_format_description *desc;
+ unsigned stride;
+
+ assert(res && res->b.b.target == PIPE_BUFFER);
+
+ desc = util_format_description(view->format);
+ stride = desc->block.bits / 8;
+
+ util_range_add(&res->valid_buffer_range,
+ stride * (view->u.buf.first_element),
+ stride * (view->u.buf.last_element + 1));
+}
+
+static void
si_set_shader_images(struct pipe_context *pipe, unsigned shader,
unsigned start_slot, unsigned count,
struct pipe_image_view *views)
@@ -513,6 +531,9 @@ si_set_shader_images(struct pipe_context *pipe, unsigned shader,
RADEON_USAGE_READWRITE);
if (res->b.b.target == PIPE_BUFFER) {
+ if (views[i].access & PIPE_IMAGE_ACCESS_WRITE)
+ si_mark_image_range_valid(&views[i]);
+
si_make_buffer_descriptor(screen, res,
views[i].format,
views[i].u.buf.first_element,
@@ -1309,6 +1330,9 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
unsigned i = u_bit_scan(&mask);
if (images->views[i].resource == buf) {
+ if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
+ si_mark_image_range_valid(&images->views[i]);
+
si_desc_reset_buffer_offset(
ctx, images->desc.list + i * 8 + 4,
old_va, buf);
commit 792a5ee42573e23e199798f488f6daf53c3a95b1
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sat May 28 14:23:35 2016 -0400
nv50/ir: record number of threads in a compute shader
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 27a51ff9b420909334898785cf194b5998776e88)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
index 35cd721..2caebe8 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
@@ -1178,6 +1178,7 @@ nv50_ir_init_prog_info(struct nv50_ir_prog_info *info)
info->prop.gp.instanceCount = 1;
info->prop.gp.maxVertices = 1;
}
+ info->prop.cp.numThreads = 1;
info->io.pointSize = 0xff;
info->io.instanceId = 0xff;
info->io.vertexId = 0xff;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index 1f7de51..b611519 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -153,6 +153,7 @@ struct nv50_ir_prog_info
uint32_t inputOffset; /* base address for user args */
uint32_t sharedOffset; /* reserved space in s[] */
uint32_t gridInfoBase; /* base address for NTID,NCTAID */
+ uint32_t numThreads; /* max number of threads */
} cp;
} prop;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 382fdb1..beb7b53 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -1002,6 +1002,7 @@ bool Source::scanSource()
}
info->io.viewportId = -1;
+ info->prop.cp.numThreads = 1;
info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
@@ -1105,7 +1106,7 @@ void Source::scanProperty(const struct tgsi_full_property *prop)
case TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH:
case TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT:
case TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH:
- // we don't care
+ info->prop.cp.numThreads *= prop->u[0].Data;
break;
case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
info->io.clipDistances = prop->u[0].Data;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.h
index 674bdc6..6bf1a5c 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.h
@@ -172,7 +172,9 @@ public:
// The address chosen is supplied to the relocation routine.
virtual void getBuiltinCode(const uint32_t **code, uint32_t *size) const = 0;
- virtual void parseDriverInfo(const struct nv50_ir_prog_info *info) { }
+ virtual void parseDriverInfo(const struct nv50_ir_prog_info *info) {
+ threads = info->prop.cp.numThreads;
+ }
virtual bool runLegalizePass(Program *, CGStage stage) const = 0;
@@ -248,6 +250,7 @@ public:
protected:
uint32_t chipset;
+ uint32_t threads;
DataFile nativeFileMap[DATA_FILE_COUNT];
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
index 2af1715..b37ea73 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
@@ -592,6 +592,8 @@ TargetNV50::parseDriverInfo(const struct nv50_ir_prog_info *info)
wposMask = 0x8;
sysvalLocation[SV_POSITION] = 0;
}
+
+ Target::parseDriverInfo(info);
}
} // namespace nv50_ir
commit 59841f5466aa1b645814ecb6bd5f3dbbee80cb99
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sat May 28 14:28:07 2016 -0400
nvc0/ir: limit max number of regs based on availability in SM
This effectively limits registers to 32 and 64 for fermi and kepler when
1024 threads are used, but allows the full amount to be used with
smaller thread sizes.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 1f895caba0accc0af3e637d6193ac0b673ce98bc)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index eb50e6d..71013eb 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -457,7 +457,7 @@ NVC0LegalizePostRA::visit(Function *fn)
pOne = new_LValue(fn, FILE_PREDICATE);
carry = new_LValue(fn, FILE_FLAGS);
- rZero->reg.data.id = prog->getTarget()->getFileSize(FILE_GPR);
+ rZero->reg.data.id = (prog->getTarget()->getChipset() >= NVISA_GK20A_CHIPSET) ? 255 : 63;
carry->reg.data.id = 0;
pOne->reg.data.id = 7;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
index fd0f894..932ec39 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
@@ -238,9 +238,11 @@ void TargetNVC0::initOpInfo()
unsigned int
TargetNVC0::getFileSize(DataFile file) const
{
+ const unsigned int gprs = (chipset >= NVISA_GK20A_CHIPSET) ? 255 : 63;
+ const unsigned int smregs = (chipset >= NVISA_GK104_CHIPSET) ? 65536 : 32768;
switch (file) {
case FILE_NULL: return 0;
- case FILE_GPR: return (chipset >= NVISA_GK20A_CHIPSET) ? 255 : 63;
+ case FILE_GPR: return MIN2(gprs, smregs / threads);
case FILE_PREDICATE: return 7;
case FILE_FLAGS: return 1;
case FILE_ADDRESS: return 0;
commit 966ee945580da266d52ec5cf53f7c4646dbf97d6
Author: Tomasz Figa <tfiga@chromium.org>
Date: Mon Jun 13 19:53:21 2016 +0900
i965: Check return value of screen->image.loader->getBuffers (v2)
The images struct is an uninitialized local variable on the stack. If the
callback returns 0, the struct might not have been updated and so should
be considered uninitialized. Currently the code ignores the return value,
which (depending on stack contents) might end up in reading a non-zero
value from images.image_mask and dereferencing further fields.
Another solution would be to initialize image_mask with 0, but checking
the return value seems more sensible and it is what Gallium is doing.
v2: fix typos in commit message,
fix indentation,
remove unnecessary parentheses and pointer dereference to keep line
length reasonable.
Cc: 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit e7ab358e8186dd8651cf920d4db1500c60ccd2fc)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 0f15414..7fde26f 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1646,6 +1646,7 @@ intel_update_image_buffers(struct brw_context *brw, __DRIdrawable *drawable)
struct __DRIimageList images;
unsigned int format;
uint32_t buffer_mask = 0;
+ int ret;
front_rb = intel_get_renderbuffer(fb, BUFFER_FRONT_LEFT);
back_rb = intel_get_renderbuffer(fb, BUFFER_BACK_LEFT);
@@ -1665,12 +1666,14 @@ intel_update_image_buffers(struct brw_context *brw, __DRIdrawable *drawable)
if (back_rb)
buffer_mask |= __DRI_IMAGE_BUFFER_BACK;
- (*screen->image.loader->getBuffers) (drawable,
- driGLFormatToImageFormat(format),
- &drawable->dri2.stamp,
- drawable->loaderPrivate,
- buffer_mask,
- &images);
+ ret = screen->image.loader->getBuffers(drawable,
+ driGLFormatToImageFormat(format),
+ &drawable->dri2.stamp,
+ drawable->loaderPrivate,
+ buffer_mask,
+ &images);
+ if (!ret)
+ return;
if (images.image_mask & __DRI_IMAGE_BUFFER_FRONT) {
drawable->w = images.front->width;
commit 8ed5204182e265ec671f24d5b15c2ef224b5a17a
Author: Dylan Baker <dylan@pnwbakers.com>
Date: Mon Jun 13 11:19:18 2016 -0700
isl: Replace bash generator with python generator
This replaces the current bash generator with a python based generator
using mako. It's quite fast and works with both python 2.7 and python
3.5, and should work with 3.3+ and maybe even 3.2.
It produces an almost identical file except for a minor layout changes,
and the addition of a "generated file, do not edit" warning.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 5a87bc718197deab7577a028c64a7f591bbfaec4)
diff --git a/src/intel/isl/Android.mk b/src/intel/isl/Android.mk
index 3134981..ff0c8c9 100644
--- a/src/intel/isl/Android.mk
+++ b/src/intel/isl/Android.mk
@@ -139,14 +139,14 @@ LOCAL_GENERATED_SOURCES += $(addprefix $(intermediates)/, $(ISL_GENERATED_FILES)
define bash-gen
@mkdir -p $(dir $@)
@echo "Gen Bash: $(PRIVATE_MODULE) <= $(notdir $(@))"
- $(hide) $(PRIVATE_SCRIPT) < $(PRIVATE_CSV) > $@
+ $(hide) $(PRIVATE_SCRIPT) --csv $(PRIVATE_CSV) --out $@
endef
isl_format_layout_deps := \
- $(LOCAL_PATH)/isl_format_layout_gen.bash \
+ $(LOCAL_PATH)/gen_format_layout.py \
$(LOCAL_PATH)/isl_format_layout.csv
-$(intermediates)/isl_format_layout.c: PRIVATE_SCRIPT := bash -c $(LOCAL_PATH)/isl_format_layout_gen.bash
+$(intermediates)/isl_format_layout.c: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/gen_format_layout.py
$(intermediates)/isl_format_layout.c: PRIVATE_CSV := $(LOCAL_PATH)/isl_format_layout.csv
$(intermediates)/isl_format_layout.c: $(isl_format_layout_deps)
$(call bash-gen)
diff --git a/src/intel/isl/Makefile.am b/src/intel/isl/Makefile.am
index 74f863a..1fd6683 100644
--- a/src/intel/isl/Makefile.am
+++ b/src/intel/isl/Makefile.am
@@ -1,4 +1,4 @@
-# Copyright 2015 Intel Corporation
+# Copyright 2015-2016 Intel Corporation
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -66,10 +66,12 @@ libisl_gen9_la_CFLAGS = $(libisl_la_CFLAGS) -DGEN_VERSIONx10=90
BUILT_SOURCES = $(ISL_GENERATED_FILES)
-isl_format_layout.c: isl_format_layout_gen.bash \
+PYTHON_GEN = $(AM_V_GEN)$(PYTHON2) $(PYTHON_FLAGS)
+
+isl_format_layout.c: gen_format_layout.py \
isl_format_layout.csv
- $(AM_V_GEN)$(srcdir)/isl_format_layout_gen.bash \
- <$(srcdir)/isl_format_layout.csv >$@
+ $(PYTHON_GEN) $(srcdir)/gen_format_layout.py \
+ --csv $(srcdir)/isl_format_layout.csv --out $@
# ----------------------------------------------------------------------------
# Tests
@@ -87,6 +89,6 @@ tests_isl_surf_get_image_offset_test_LDADD = \
# ----------------------------------------------------------------------------
EXTRA_DIST = \
- isl_format_layout_gen.bash \
+ gen_format_layout.py \
isl_format_layout.csv \
README
diff --git a/src/intel/isl/gen_format_layout.py b/src/intel/isl/gen_format_layout.py
new file mode 100644
index 0000000..d7f3900
--- /dev/null
+++ b/src/intel/isl/gen_format_layout.py
@@ -0,0 +1,207 @@
+# encoding=utf-8
+# Copyright © 2016 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+"""Generates isl_format_layout.c."""
+
+from __future__ import absolute_import, division, print_function
+import argparse
+import csv
+import re
+import textwrap
+
+from mako import template
+
+# Load the template, ensure that __future__.division is imported, and set the
+# bytes encoding to be utf-8. This last bit is important to getting simple
+# consistent behavior for python 3 when we get there.
+TEMPLATE = template.Template(
+ text=textwrap.dedent("""\
+ /* This file is autogenerated by gen_format_layout.py. DO NOT EDIT! */
+
+ /*
+ * Copyright 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+ #include "isl.h"
+
+ const struct isl_format_layout
+ isl_format_layouts[] = {
+ % for format in formats:
+ [ISL_FORMAT_${format.name}] = {
+ .format = ISL_FORMAT_${format.name},
+ .name = "ISL_FORMAT_${format.name}",
+ .bs = ${format.bs},
+ .bw = ${format.bw},
+ .bh = ${format.bh},
+ .bd = ${format.bd},
+ .channels = {
+ % for mask in ['r', 'g', 'b', 'a', 'l', 'i', 'p']:
+ <% channel = getattr(format, mask, None) %>\\
+ % if channel.type is not None:
+ .${mask} = { ISL_${channel.type}, ${channel.size} },
+ % else:
+ .${mask} = {},
+ % endif
+ % endfor
+ },
+ .colorspace = ISL_COLORSPACE_${format.colorspace},
+ .txc = ISL_TXC_${format.txc},
+ },
+
+ % endfor
+ };
+ """),
+ future_imports=['division'],
+ output_encoding='utf-8')
+
+
+class Channel(object):
+ """Class representing a Channel.
+
+ Converts the csv encoded data into the format that the template (and thus
+ the consuming C code) expects.
+
+ """
+ # If the csv file grew very large this class could be put behind a factory
+ # to increase efficiency. Right now though it's fast enough that It didn't
+ # seem worthwhile to add all of the boilerplate
+ _types = {
+ 'x': 'void',
+ 'r': 'raw',
+ 'un': 'unorm',
+ 'sn': 'snorm',
+ 'uf': 'ufloat',
+ 'sf': 'sfloat',
+ 'ux': 'ufixed',
+ 'sx': 'sfixed',
+ 'ui': 'uint',
+ 'si': 'sint',
+ 'us': 'uscaled',
+ 'ss': 'sscaled',
+ }
+ _splitter = re.compile(r'\s*(?P<type>[a-z]+)(?P<size>[0-9]+)')
+
+ def __init__(self, line):
+ # If the line is just whitespace then just set everything to None to
+ # save on the regex cost and let the template skip on None.
+ if line.isspace():
+ self.size = None
+ self.type = None
+ else:
+ grouped = self._splitter.match(line)
+ self.type = self._types[grouped.group('type')].upper()
+ self.size = grouped.group('size')
+
+
+class Format(object):
+ """Class taht contains all values needed by the template."""
+ def __init__(self, line):
+ # pylint: disable=invalid-name
+ self.name = line[0].strip()
+
+ # Future division makes this work in python 2.
+ self.bs = int(line[1]) // 8
+ self.bw = line[2].strip()
+ self.bh = line[3].strip()
+ self.bd = line[4].strip()
+ self.r = Channel(line[5])
+ self.g = Channel(line[6])
+ self.b = Channel(line[7])
+ self.a = Channel(line[8])
+ self.l = Channel(line[9])
+ self.i = Channel(line[10])
+ self.p = Channel(line[11])
+
+ # alpha doesn't have a colorspace of it's own.
+ self.colorspace = line[12].strip().upper()
+ if self.colorspace in ['', 'ALPHA']:
+ self.colorspace = 'NONE'
+
+ # This sets it to the line value, or if it's an empty string 'NONE'
+ self.txc = line[13].strip().upper() or 'NONE'
+
+
+def reader(csvfile):
+ """Wrapper around csv.reader that skips comments and blanks."""
+ # csv.reader actually reads the file one line at a time (it was designed to
+ # open excel generated sheets), so hold the file until all of the lines are
+ # read.
+ with open(csvfile, 'r') as f:
+ for line in csv.reader(f):
+ if line and not line[0].startswith('#'):
+ yield line
+
+
+def main():
+ """Main function."""
+ parser = argparse.ArgumentParser()
+ parser.add_argument('--csv', action='store', help='The CSV file to parse.')
+ parser.add_argument(
+ '--out',
+ action='store',
+ help='The location to put the generated C file.')
+ args = parser.parse_args()
+
+ # This generator opens and writes the file itself, and it does so in bytes
+ # mode. This solves both python 2 vs 3 problems and solves the locale
+ # problem: Unicode can be rendered even if the shell calling this script
+ # doesn't.
+ with open(args.out, 'wb') as f:
+ try:
+ # This basically does lazy evaluation and initialization, which
+ # saves on memory and startup overhead.
+ f.write(TEMPLATE.render(
+ formats=(Format(l) for l in reader(args.csv))))
+ except Exception:
+ # In the even there's an error this imports some helpers from mako
+ # to print a useful stack trace and prints it, then exits with
+ # status 1, if python is run with debug; otherwise it just raises
+ # the exception
+ if __debug__:
+ import sys
+ from mako import exceptions
+ print(exceptions.text_error_template().render(),
+ file=sys.stderr)
+ sys.exit(1)
+ raise
+
+
+if __name__ == '__main__':
+ main()
diff --git a/src/intel/isl/isl_format_layout_gen.bash b/src/intel/isl/isl_format_layout_gen.bash
deleted file mode 100755
index e20da55..0000000
--- a/src/intel/isl/isl_format_layout_gen.bash
+++ /dev/null
@@ -1,129 +0,0 @@
-#!/usr/bin/env bash
-#
-# Copyright 2015 Intel Corporation
-#
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the "Software"),
-# to deal in the Software without restriction, including without limitation
-# the rights to use, copy, modify, merge, publish, distribute, sublicense,
-# and/or sell copies of the Software, and to permit persons to whom the
-# Software is furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice (including the next
-# paragraph) shall be included in all copies or substantial portions of the
-# Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-# IN THE SOFTWARE.
-
-set -eu
-set -o pipefail
-
-cat <<'EOF'
-/*
- * Copyright 2015 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include "isl.h"
-
-const struct isl_format_layout
-isl_format_layouts[] = {
-EOF
-
-sed -r '
-# Delete comment lines and empty lines
-/^[[:space:]]*#/d
-/^[[:space:]]*$/d
-
-# Delete spaces
-s/[[:space:]]//g
-
-# Translate formats
-s/^([A-Za-z0-9_]+),*/ISL_FORMAT_\1,/
-
-# Translate data type of channels
-s/\<x([0-9]+),/ISL_VOID@\1,/g
-s/\<r([0-9]+),/ISL_RAW@\1,/g
-s/\<un([0-9]+),/ISL_UNORM@\1,/g
-s/\<sn([0-9]+),/ISL_SNORM@\1,/g
-s/\<uf([0-9]+),/ISL_UFLOAT@\1,/g
-s/\<sf([0-9]+),/ISL_SFLOAT@\1,/g
-s/\<ux([0-9]+),/ISL_UFIXED@\1,/g
-s/\<sx([0-9]+),/ISL_SFIXED@\1,/g
-s/\<ui([0-9]+),/ISL_UINT@\1,/g
-s/\<si([0-9]+),/ISL_SINT@\1,/g
-s/\<us([0-9]+),/ISL_USCALED@\1,/g
-s/\<ss([0-9]+),/ISL_SSCALED@\1,/g
-
-# Translate colorspaces
-# Interpret alpha-only formats as having no colorspace.
-s/\<(linear|srgb|yuv)\>/ISL_COLORSPACE_\1/
-s/\<alpha\>//
-
-# Translate texture compression
-s/\<(dxt|fxt|rgtc|bptc|etc|astc)([0-9]*)\>/ISL_TXC_\1\2/
-' |
-tr 'a-z' 'A-Z' | # Convert to uppersace
-while IFS=, read -r format bpb bw bh bd \
- red green blue alpha \
- luminance intensity palette \
- colorspace txc
-do
- : ${colorspace:=ISL_COLORSPACE_NONE}
- : ${txc:=ISL_TXC_NONE}
-
- cat <<EOF
- [$format] = {
- .format = $format,
- .name = "$format",
- .bs = $((bpb/8)),
- .bw = $bw, .bh = $bh, .bd = $bd,
- .channels = {
- .r = { $red },
- .g = { $green },
- .b = { $blue },
- .a = { $alpha },
- .l = { $luminance },
- .i = { $intensity },
- .p = { $palette },
- },
- .colorspace = $colorspace,
- .txc = $txc,
- },
-
-EOF
-done |
-sed -r '
-# Collapse empty channels
-s/\{ \}/{}/
-
-# Split non-empty channels into two members: base type and bit size
-s/@/, /
-'
-
-# Terminate the table
-printf '};\n'
commit 28294573c737ff762b1c3f8d58bc78ddd010feca
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Mon Jun 6 22:49:57 2016 +0200
radeonsi: Reinitialize all descriptors in CE preamble.
This fixes a problem with the CE preamble and restoring only stuff in the
preamble when needed.
To illustrate suppose we have two graphics IB's 1 and 2, which are submitted in
that order. Furthermore suppose IB 1 does not use CE ram, but IB 2 does, and we
have a context switch at the start of IB 1, but not between IB 1 and IB 2.
The old code put the CE RAM loads in the preamble of IB 2. As the preamble of
IB 1 does not have the loads and the preamble of IB 2 does not get executed, the
old values are not load into CE RAM.
Fix this by always restoring the entire CE RAM.
v2: - Just load all descriptor set buffers instead of load and store the entire
CE RAM.
- Leave the ce_ram_dirty tracking in place for the non-preamble case.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Note: This commit differs from the one in master - 54f755fa0fd
("radeonsi: Reinitialize all descriptors in CE preamble.")
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 69fdb08..57d2ae6 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -159,7 +159,7 @@ static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned s
return true;
}
-static void si_reinitialize_ce_ram(struct si_context *sctx,
+static void si_ce_reinitialize_descriptors(struct si_context *sctx,
struct si_descriptors *desc)
{
if (desc->buffer) {
@@ -185,6 +185,17 @@ static void si_reinitialize_ce_ram(struct si_context *sctx,
desc->ce_ram_dirty = false;
}
+void si_ce_reinitialize_all_descriptors(struct si_context *sctx)
+{
+ for (int i = 0; i < SI_NUM_SHADERS; i++) {
+ si_ce_reinitialize_descriptors(sctx, &sctx->const_buffers[i].desc);
+ si_ce_reinitialize_descriptors(sctx, &sctx->shader_buffers[i].desc);
+ si_ce_reinitialize_descriptors(sctx, &sctx->samplers[i].views.desc);
+ si_ce_reinitialize_descriptors(sctx, &sctx->images[i].desc);
+ }
+ si_ce_reinitialize_descriptors(sctx, &sctx->rw_buffers.desc);
+}
+
void si_ce_enable_loads(struct radeon_winsys_cs *ib)
{
radeon_emit(ib, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
@@ -206,7 +217,7 @@ static bool si_upload_descriptors(struct si_context *sctx,
uint32_t const* list = (uint32_t const*)desc->list;
if (desc->ce_ram_dirty)
- si_reinitialize_ce_ram(sctx, desc);
+ si_ce_reinitialize_descriptors(sctx, desc);
while(desc->dirty_mask) {
int begin, count;
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index dcf206d..1a887c1 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -207,6 +207,9 @@ void si_begin_new_cs(struct si_context *ctx)
else if (ctx->ce_ib)
si_ce_enable_loads(ctx->ce_ib);
+ if (ctx->ce_preamble_ib)
+ si_ce_reinitialize_all_descriptors(ctx);
+
ctx->framebuffer.dirty_cbufs = (1 << 8) - 1;
ctx->framebuffer.dirty_zsbuf = true;
si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index a3589d4..aea98ae 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -250,6 +250,7 @@ struct si_buffer_resources {
} while(0)
/* si_descriptors.c */
+void si_ce_reinitialize_all_descriptors(struct si_context *sctx);
void si_ce_enable_loads(struct radeon_winsys_cs *ib);
void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
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