mesa: Changes to 'ubuntu+1'
VERSION | 2
configure.ac | 145 ----
debian/changelog | 17
debian/libegl1-mesa.symbols | 3
debian/mesa-common-dev.docs | 12
debian/source/local-options | 2
docs/relnotes/10.6.1.html | 3
docs/relnotes/10.6.2.html | 165 +++++
docs/relnotes/10.6.3.html | 105 +++
src/gallium/auxiliary/vl/vl_mpeg12_decoder.c | 24
src/gallium/auxiliary/vl/vl_mpeg12_decoder.h | 4
src/gallium/auxiliary/vl/vl_winsys_dri.c | 17
src/gallium/drivers/nouveau/codegen/nv50_ir_bb.cpp | 3
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 10
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 12
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 6
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp | 1
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 42 +
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 5
src/gallium/drivers/nouveau/nv50/nv50_state_validate.c | 18
src/gallium/drivers/nouveau/nv50/nv50_tex.c | 11
src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c | 18
src/gallium/drivers/nouveau/nvc0/nvc0_surface.c | 7
src/gallium/drivers/r600/r600_blit.c | 7
src/gallium/drivers/radeonsi/si_state_draw.c | 4
src/gallium/state_trackers/dri/dri2.c | 2
src/gallium/state_trackers/osmesa/osmesa.c | 2
src/gallium/state_trackers/vdpau/mixer.c | 22
src/gallium/state_trackers/xa/xa_context.c | 6
src/gallium/state_trackers/xa/xa_tracker.c | 2
src/gallium/state_trackers/xa/xa_yuv.c | 2
src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c | 6
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 28
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 17
src/gallium/winsys/radeon/drm/radeon_drm_winsys.h | 1
src/glsl/ast_array_index.cpp | 38 -
src/glsl/linker.cpp | 77 ++
src/glsl/loop_unroll.cpp | 12
src/glsl/opt_algebraic.cpp | 4
src/loader/loader.c | 46 -
src/mesa/Makefile.am | 5
src/mesa/drivers/common/meta.c | 4
src/mesa/drivers/dri/i915/i915_context.c | 3
src/mesa/drivers/dri/i965/brw_context.c | 4
src/mesa/drivers/dri/i965/brw_context.h | 1
src/mesa/drivers/dri/i965/brw_defines.h | 12
src/mesa/drivers/dri/i965/brw_fs.cpp | 20
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 19
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 7
src/mesa/drivers/dri/i965/brw_program.c | 11
src/mesa/drivers/dri/i965/gen6_cc.c | 2
src/mesa/drivers/dri/i965/gen8_ps_state.c | 3
src/mesa/drivers/dri/i965/gen8_surface_state.c | 3
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 4
src/mesa/drivers/osmesa/osmesa.c | 2
src/mesa/main/mtypes.h | 1
src/mesa/main/texstore.c | 1
src/mesa/program/prog_opt_constant_fold.c | 2
src/mesa/program/program_parse_extra.c | 50 +
src/mesa/state_tracker/st_context.c | 5
src/util/Makefile.am | 7
src/util/Makefile.sources | 4
src/util/SConscript | 5
src/util/mesa-sha1.c | 316 ----------
src/util/mesa-sha1.h | 53 -
65 files changed, 783 insertions(+), 669 deletions(-)
New commits:
commit 30b98e8f2120d491fa5282cb307d5ebaa186cbd7
Author: Timo Aaltonen <tjaalton@debian.org>
Date: Tue Jul 28 12:44:36 2015 +0300
update the changelog
diff --git a/debian/changelog b/debian/changelog
index 31dd195..6b5cbc9 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,11 @@
+mesa (10.6.3-0ubuntu1) UNRELEASED; urgency=medium
+
+ * Merge from debian-experimental git.
+ * Drop skl-*, i965-* patches, upstream.
+ * egl-platform-mir.patch: Updated.
+
+ -- Timo Aaltonen <tjaalton@debian.org> Thu, 18 Jun 2015 15:31:27 +0300
+
mesa (10.6.3-1) unstable; urgency=medium
* New upstream release.
@@ -11,14 +19,6 @@ mesa (10.6.3-1) unstable; urgency=medium
-- Timo Aaltonen <tjaalton@debian.org> Tue, 28 Jul 2015 11:12:44 +0300
-mesa (10.6.1-0ubuntu1) UNRELEASED; urgency=medium
-
- * Merge from debian-experimental git.
- * Drop skl-*, i965-* patches, upstream.
- * egl-platform-mir.patch: Updated.
-
- -- Timo Aaltonen <tjaalton@debian.org> Thu, 18 Jun 2015 15:31:27 +0300
-
mesa (10.5.9-2) unstable; urgency=medium
* i965-do_blit_drawpixels-decode-array-formats.patch: Fix a regression
commit e94d6b3145be057ce335d5e7d714cf8677aa46a6
Author: Timo Aaltonen <tjaalton@debian.org>
Date: Tue Jul 28 11:13:39 2015 +0300
upload to sid
diff --git a/debian/changelog b/debian/changelog
index 1fad33a..bed0c7c 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-mesa (10.6.3-1) UNRELEASED; urgency=medium
+mesa (10.6.3-1) unstable; urgency=medium
* New upstream release.
* libegl1-mesa.symbols: Updated.
@@ -9,7 +9,7 @@ mesa (10.6.3-1) UNRELEASED; urgency=medium
* mesa-common-dev.docs: Updated.
* Delete i965-do_blit...patch, upstream.
- -- Timo Aaltonen <tjaalton@debian.org> Mon, 27 Apr 2015 10:43:45 +0300
+ -- Timo Aaltonen <tjaalton@debian.org> Tue, 28 Jul 2015 11:12:44 +0300
mesa (10.5.9-2) unstable; urgency=medium
commit 5a0ef49e39016596ac7be37782288424cac9f6ea
Author: Timo Aaltonen <tjaalton@debian.org>
Date: Tue Jul 28 11:12:36 2015 +0300
Delete i965-do_blit...patch, upstream.
diff --git a/debian/changelog b/debian/changelog
index fa1efeb..1fad33a 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -7,6 +7,7 @@ mesa (10.6.3-1) UNRELEASED; urgency=medium
* libegl1-mesa.symbols: Drop a spurious comment.
* source/local-options: Updated extend-diff-ignore.
* mesa-common-dev.docs: Updated.
+ * Delete i965-do_blit...patch, upstream.
-- Timo Aaltonen <tjaalton@debian.org> Mon, 27 Apr 2015 10:43:45 +0300
diff --git a/debian/patches/i965-do_blit_drawpixels-decode-array-formats.patch b/debian/patches/i965-do_blit_drawpixels-decode-array-formats.patch
deleted file mode 100644
index 5808155..0000000
--- a/debian/patches/i965-do_blit_drawpixels-decode-array-formats.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-commit bd38f91f8d80897ca91979962d80d4bc0acef586
-Author: Alexander Monakov <amonakov@gmail.com>
-Date: Tue Jun 9 20:58:22 2015 +0300
-
- i965: do_blit_drawpixels: decode array formats
-
- Correct a regression introduced by commit 922c0c9fd526 by converting "array
- format", if received from _mesa_format_from_format_and_type, to mesa_format.
-
- References: https://bugs.freedesktop.org/show_bug.cgi?id=90839
- Signed-off-by: Alexander Monakov <amonakov@gmail.com>
- Tested-by: AnAkkk <anakin.cs@gmail.com>
- Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
- Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
- Cc: mesa-stable@lists.freedesktop.org
-
-diff --git a/src/mesa/drivers/dri/i965/intel_pixel_draw.c b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
-index d68cbb6..189a592 100644
---- a/src/mesa/drivers/dri/i965/intel_pixel_draw.c
-+++ b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
-@@ -78,6 +78,8 @@ do_blit_drawpixels(struct gl_context * ctx,
- struct intel_renderbuffer *irb = intel_renderbuffer(rb);
-
- mesa_format src_format = _mesa_format_from_format_and_type(format, type);
-+ if (_mesa_format_is_mesa_array_format(src_format))
-+ src_format = _mesa_format_from_array_format(src_format);
- mesa_format dst_format = irb->mt->format;
-
- /* We can safely discard sRGB encode/decode for the DrawPixels interface */
diff --git a/debian/patches/series b/debian/patches/series
index 11e1fc6..9f0749f 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -1,2 +1 @@
07_gallium-fix-build-failure-on-powerpcspe.diff
-i965-do_blit_drawpixels-decode-array-formats.patch
commit eae988278aaca4a7ad00ce147eaae704fab017cc
Author: Timo Aaltonen <tjaalton@debian.org>
Date: Tue Jul 28 10:55:05 2015 +0300
update changelog
diff --git a/debian/changelog b/debian/changelog
index 27ca1a7..a20db6e 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-mesa (10.6.2-1) UNRELEASED; urgency=medium
+mesa (10.6.3-1) UNRELEASED; urgency=medium
* New upstream release.
* libegl1-mesa.symbols: Updated.
commit ddc976368fef367e464472ebcc2ac4fd89eb9fd8
Author: Emil Velikov <emil.l.velikov@gmail.com>
Date: Sun Jul 26 14:38:58 2015 +0100
Add release notes for 10.6.3
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
diff --git a/docs/relnotes/10.6.3.html b/docs/relnotes/10.6.3.html
new file mode 100644
index 0000000..831af48
--- /dev/null
+++ b/docs/relnotes/10.6.3.html
@@ -0,0 +1,105 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.6.3 Release Notes / July 26, 2015</h1>
+
+<p>
+Mesa 10.6.3 is a bug fix release which fixes bugs found since the 10.6.2 release.
+</p>
+<p>
+Mesa 10.6.3 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3. OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=90728";>Bug 90728</a> - dvd playback with vlc and vdpau causes segmentation fault</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=91337";>Bug 91337</a> - OSMesaGetProcAdress("OSMesaPixelStore") returns nil</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Brian Paul (1):</p>
+<ul>
+ <li>osmesa: fix OSMesaPixelsStore typo</li>
+</ul>
+
+<p>Chad Versace (1):</p>
+<ul>
+ <li>mesa: Fix generation of git_sha1.h.tmp for gitlinks</li>
+</ul>
+
+<p>Christian König (2):</p>
+<ul>
+ <li>vl: cleanup video buffer private when the decoder is destroyed</li>
+ <li>st/vdpau: fix mixer size checks</li>
+</ul>
+
+<p>Emil Velikov (3):</p>
+<ul>
+ <li>docs: Add sha256 checksums for the 10.6.2 release</li>
+ <li>auxiliary/vl: use the correct screen index</li>
+ <li>Update version to 10.6.3</li>
+</ul>
+
+<p>Francisco Jerez (1):</p>
+<ul>
+ <li>i965/gen9: Use custom MOCS entries set up by the kernel.</li>
+</ul>
+
+<p>Ilia Mirkin (5):</p>
+<ul>
+ <li>nv50, nvc0: enable at least one color RT if alphatest is enabled</li>
+ <li>nvc0/ir: fix txq on indirect samplers</li>
+ <li>nvc0/ir: don't worry about sampler in txq handling</li>
+ <li>gm107/ir: fix indirect txq emission</li>
+ <li>nv50: fix max level clamping on G80</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+ <li>program: Allow redundant OPTION ARB_fog_* directives.</li>
+</ul>
+
+<p>Rob Clark (1):</p>
+<ul>
+ <li>xa: don't leak fences</li>
+</ul>
+
+
+</div>
+</body>
+</html>
commit 2eef0b7d8608faeecd7cf71b386d64edd7a08e24
Author: Emil Velikov <emil.l.velikov@gmail.com>
Date: Sun Jul 26 14:33:29 2015 +0100
Update version to 10.6.3
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
diff --git a/VERSION b/VERSION
index 6842906..15c6f3e 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-10.6.2
+10.6.3
commit cb1bfb58caddd129146c738ac3efb44ce2d3fcda
Author: Timo Aaltonen <tjaalton@debian.org>
Date: Fri Jul 24 15:17:18 2015 +0300
bump the version
diff --git a/debian/changelog b/debian/changelog
index 9e1f798..27ca1a7 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-mesa (10.6.1-1) UNRELEASED; urgency=medium
+mesa (10.6.2-1) UNRELEASED; urgency=medium
* New upstream release.
* libegl1-mesa.symbols: Updated.
commit 954c18fb5c95c125ef43a88b55af620dca32e829
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Mon Jul 20 00:19:56 2015 -0400
nv50: fix max level clamping on G80
It appears that the G80 did not have support for the sampler view
first/last clamping. Put the view's last level in the place of the
texture's so that it doesn't go past what the sampler view allows.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 801d41fa43eba996c6bd7c071282ad15e51609d3)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_tex.c b/src/gallium/drivers/nouveau/nv50/nv50_tex.c
index d69c8d6..17ae27f 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_tex.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_tex.c
@@ -71,6 +71,7 @@ nv50_create_texture_view(struct pipe_context *pipe,
uint32_t flags,
enum pipe_texture_target target)
{
+ const uint32_t class_3d = nouveau_context(pipe)->screen->class_3d;
const struct util_format_description *desc;
uint64_t addr;
uint32_t *tic;
@@ -201,11 +202,17 @@ nv50_create_texture_view(struct pipe_context *pipe,
tic[5] = (mt->base.base.height0 << mt->ms_y) & 0xffff;
tic[5] |= depth << 16;
- tic[5] |= mt->base.base.last_level << NV50_TIC_5_LAST_LEVEL__SHIFT;
+ if (class_3d > NV50_3D_CLASS)
+ tic[5] |= mt->base.base.last_level << NV50_TIC_5_LAST_LEVEL__SHIFT;
+ else
+ tic[5] |= view->pipe.u.tex.last_level << NV50_TIC_5_LAST_LEVEL__SHIFT;
tic[6] = (mt->ms_x > 1) ? 0x88000000 : 0x03000000; /* sampling points */
- tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level;
+ if (class_3d > NV50_3D_CLASS)
+ tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level;
+ else
+ tic[7] = 0;
if (unlikely(!(tic[2] & NV50_TIC_2_NORMALIZED_COORDS)))
if (mt->base.base.last_level)
commit 2a77b82a92494d91e90b516ad5fed8e6e0a10a6b
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sat Jul 18 19:02:29 2015 -0400
gm107/ir: fix indirect txq emission
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 8c8a71f0d125bb655b17a32914ffecf8d159593b)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 22db368..689e2bb 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -2437,8 +2437,14 @@ CodeEmitterGM107::emitTXQ()
break;
}
- emitInsn (0xdf4a0000);
- emitField(0x24, 13, insn->tex.r);
+ if (insn->tex.rIndirectSrc >= 0) {
+ emitInsn (0xdf500000);
+ } else {
+ emitInsn (0xdf480000);
+ emitField(0x24, 13, insn->tex.r);
+ }
+
+ emitField(0x31, 1, insn->tex.liveOnly);
emitField(0x1f, 4, insn->tex.mask);
emitField(0x16, 6, type);
emitGPR (0x08, insn->src(0));
commit 7efc693ef26c91c545c78f4b751432e43011b541
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sat Jul 18 18:38:42 2015 -0400
nvc0/ir: don't worry about sampler in txq handling
There's no need to deal with samplers for texture size queries. That
code also was accidentally setting an invalid sIndirectSrc position, but
it can now just be removed.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 346ce0b98832e33d5411200002571b3edea9e2bb)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index da364f2..e71fa11 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -956,44 +956,30 @@ NVC0LoweringPass::handleTXD(TexInstruction *txd)
bool
NVC0LoweringPass::handleTXQ(TexInstruction *txq)
{
- if (txq->tex.rIndirectSrc < 0 && txq->tex.sIndirectSrc < 0)
+ if (txq->tex.rIndirectSrc < 0)
return true;
Value *ticRel = txq->getIndirectR();
- Value *tscRel = txq->getIndirectS();
const int chipset = prog->getTarget()->getChipset();
txq->setIndirectS(NULL);
txq->tex.sIndirectSrc = -1;
+ assert(ticRel);
+
if (chipset < NVISA_GK104_CHIPSET) {
LValue *src = new_LValue(func, FILE_GPR); // 0xttxsaaaa
- if (ticRel) {
- txq->setSrc(txq->tex.rIndirectSrc, NULL);
- if (txq->tex.r)
- ticRel = bld.mkOp2v(OP_ADD, TYPE_U32, bld.getScratch(),
- ticRel, bld.mkImm(txq->tex.r));
- }
- if (tscRel) {
- txq->setSrc(txq->tex.sIndirectSrc, NULL);
- if (txq->tex.s)
- tscRel = bld.mkOp2v(OP_ADD, TYPE_U32, bld.getScratch(),
- tscRel, bld.mkImm(txq->tex.s));
- }
-
- bld.loadImm(src, 0);
+ txq->setSrc(txq->tex.rIndirectSrc, NULL);
+ if (txq->tex.r)
+ ticRel = bld.mkOp2v(OP_ADD, TYPE_U32, bld.getScratch(),
+ ticRel, bld.mkImm(txq->tex.r));
- if (ticRel)
- bld.mkOp3(OP_INSBF, TYPE_U32, src, ticRel, bld.mkImm(0x0917), src);
- if (tscRel)
- bld.mkOp3(OP_INSBF, TYPE_U32, src, tscRel, bld.mkImm(0x0710), src);
+ bld.mkOp2(OP_SHL, TYPE_U32, src, ticRel, bld.mkImm(0x17));
txq->moveSources(0, 1);
txq->setSrc(0, src);
} else {
- // XXX this ignores tsc, and assumes a 1:1 mapping
- assert(txq->tex.rIndirectSrc >= 0);
Value *hnd = loadTexHandle(
bld.mkOp2v(OP_SHL, TYPE_U32, bld.getSSA(),
txq->getIndirectR(), bld.mkImm(2)),
commit 440f465f5f38c0f522eea3a79d94663954b63864
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sat Jul 18 16:43:17 2015 -0400
nvc0/ir: fix txq on indirect samplers
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 20e484afa4874e87cd18daffd66286bb893cf3fb)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index c0cbfeb..d81ec90 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -1739,7 +1739,7 @@ Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
}
tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
- setTexRS(tex, c, 1, -1);
+ setTexRS(tex, ++c, 1, -1);
bb->insertTail(tex);
}
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 7a5d1ce..da364f2 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -956,7 +956,61 @@ NVC0LoweringPass::handleTXD(TexInstruction *txd)
bool
NVC0LoweringPass::handleTXQ(TexInstruction *txq)
{
- // TODO: indirect resource/sampler index
+ if (txq->tex.rIndirectSrc < 0 && txq->tex.sIndirectSrc < 0)
+ return true;
+
+ Value *ticRel = txq->getIndirectR();
+ Value *tscRel = txq->getIndirectS();
+ const int chipset = prog->getTarget()->getChipset();
+
+ txq->setIndirectS(NULL);
+ txq->tex.sIndirectSrc = -1;
+
+ if (chipset < NVISA_GK104_CHIPSET) {
+ LValue *src = new_LValue(func, FILE_GPR); // 0xttxsaaaa
+
+ if (ticRel) {
+ txq->setSrc(txq->tex.rIndirectSrc, NULL);
+ if (txq->tex.r)
+ ticRel = bld.mkOp2v(OP_ADD, TYPE_U32, bld.getScratch(),
+ ticRel, bld.mkImm(txq->tex.r));
+ }
+ if (tscRel) {
+ txq->setSrc(txq->tex.sIndirectSrc, NULL);
+ if (txq->tex.s)
+ tscRel = bld.mkOp2v(OP_ADD, TYPE_U32, bld.getScratch(),
+ tscRel, bld.mkImm(txq->tex.s));
+ }
+
+ bld.loadImm(src, 0);
+
+ if (ticRel)
+ bld.mkOp3(OP_INSBF, TYPE_U32, src, ticRel, bld.mkImm(0x0917), src);
+ if (tscRel)
+ bld.mkOp3(OP_INSBF, TYPE_U32, src, tscRel, bld.mkImm(0x0710), src);
+
+ txq->moveSources(0, 1);
+ txq->setSrc(0, src);
+ } else {
+ // XXX this ignores tsc, and assumes a 1:1 mapping
+ assert(txq->tex.rIndirectSrc >= 0);
+ Value *hnd = loadTexHandle(
+ bld.mkOp2v(OP_SHL, TYPE_U32, bld.getSSA(),
+ txq->getIndirectR(), bld.mkImm(2)),
+ txq->tex.r);
+ txq->tex.r = 0xff;
+ txq->tex.s = 0x1f;
+
+ if (chipset < NVISA_GM107_CHIPSET) {
+ txq->setIndirectR(NULL);
+ txq->moveSources(0, 1);
+ txq->setSrc(0, hnd);
+ txq->tex.rIndirectSrc = 0;
+ } else {
+ txq->setIndirectR(hnd);
+ }
+ }
+
return true;
}
commit 9656b34faef3a262ad0354a3194ed1ee1edd1e16
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Sat Jul 4 19:15:16 2015 -0700
program: Allow redundant OPTION ARB_fog_* directives.
A fragment program from "Pixel Piracy" contains redundant OPTION
directives:
!!ARBfp1.0
OPTION ARB_precision_hint_fastest;
OPTION ARB_fog_exp2;
OPTION ARB_precision_hint_fastest;
OPTION ARB_fog_exp2;
...
We already allow redundant ARB_precision_hint_fastest directives, but
disallow the redundant (yet consistent) ARB_fog_exp2 directives, failing
to compile the program.
The specification seems to contradict itself - the main text says that
only one fog application option may be specified, but then backpedals,
indicating the intent is to disallow /contradictory/ flags. One of the
issues suggests that specifying contradictory ones is stupid, but
allowed, and only the last one should take effect.
Accepting multiple redundant (but consistent) directives seems harmless,
and like a reasonable interpretation of the specification. It also
fixes a fragment program found in the wild.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit 4b17f0d9f58637300b0748d1fb702a7e4d51979f)
diff --git a/src/mesa/program/program_parse_extra.c b/src/mesa/program/program_parse_extra.c
index a9e3640..043c29d 100644
--- a/src/mesa/program/program_parse_extra.c
+++ b/src/mesa/program/program_parse_extra.c
@@ -163,6 +163,8 @@ _mesa_ARBvp_parse_option(struct asm_parser_state *state, const char *option)
int
_mesa_ARBfp_parse_option(struct asm_parser_state *state, const char *option)
{
+ unsigned fog_option;
+
/* All of the options currently supported start with "ARB_". The code is
* currently structured with nested if-statements because eventually options
* that start with "NV_" will be supported. This structure will result in
@@ -177,20 +179,42 @@ _mesa_ARBfp_parse_option(struct asm_parser_state *state, const char *option)
if (strncmp(option, "fog_", 4) == 0) {
option += 4;
- if (state->option.Fog == OPTION_NONE) {
- if (strcmp(option, "exp") == 0) {
- state->option.Fog = OPTION_FOG_EXP;
- return 1;
- } else if (strcmp(option, "exp2") == 0) {
- state->option.Fog = OPTION_FOG_EXP2;
- return 1;
- } else if (strcmp(option, "linear") == 0) {
- state->option.Fog = OPTION_FOG_LINEAR;
- return 1;
- }
- }
+ if (strcmp(option, "exp") == 0) {
+ fog_option = OPTION_FOG_EXP;
+ } else if (strcmp(option, "exp2") == 0) {
+ fog_option = OPTION_FOG_EXP2;
+ } else if (strcmp(option, "linear") == 0) {
+ fog_option = OPTION_FOG_LINEAR;
+ } else {
+ /* invalid option */
+ return 0;
+ }
- return 0;
+ if (state->option.Fog == OPTION_NONE) {
+ state->option.Fog = fog_option;
+ return 1;
+ }
+
+ /* The ARB_fragment_program specification instructs us to handle
+ * redundant options in two seemingly contradictory ways:
+ *
+ * Section 3.11.4.5.1 says:
+ * "Only one fog application option may be specified by any given
+ * fragment program. A fragment program that specifies more than one
+ * of the program options "ARB_fog_exp", "ARB_fog_exp2", and
+ * "ARB_fog_linear", will fail to load."
+ *
+ * Issue 27 says:
+ * "The three mandatory options are ARB_fog_exp, ARB_fog_exp2, and
+ * ARB_fog_linear. As these options are mutually exclusive by
+ * nature, specifying more than one is not useful. If more than one
+ * is specified, the last one encountered in the <optionSequence>
+ * will be the one to actually modify the execution environment."
+ *
+ * We choose to allow programs to specify the same OPTION redundantly,
+ * but fail to load programs that specify contradictory options.
+ */
+ return state->option.Fog == fog_option ? 1 : 0;
} else if (strncmp(option, "precision_hint_", 15) == 0) {
option += 15;
commit 329763791b2a869f30a39b8d1f94b95dcb2c9e8e
Author: Francisco Jerez <currojerez@riseup.net>
Date: Wed Jul 1 16:32:24 2015 +0300
i965/gen9: Use custom MOCS entries set up by the kernel.
Instead of relying on hardware defaults the i915 kernel driver is
going program custom MOCS tables system-wide on Gen9 hardware. The
"WT" entry previously used for renderbuffers had a number of problems:
It disabled caching on eLLC, it used a reserved L3 cacheability
setting, and it used to override the PTE controls making renderbuffers
always WT on LLC regardless of the kernel's setting. Instead use an
entry from the new MOCS tables with parameters: TC=LLC/eLLC, LeCC=PTE,
L3CC=WB.
The "WB" entry previously used for anything other than renderbuffers
has moved to a different index in the new MOCS tables but it should
have the same caching semantics as the old entry.
Even though the corresponding kernel change ("drm/i915: Added
Programming of the MOCS") is in a way an ABI break it doesn't seem
necessary to check that the kernel is recent enough because the change
should only affect Gen9 which is still unreleased hardware.
v2: Update MOCS values for the new Android-incompatible tables
introduced in v7 of the kernel patch.
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Reference: http://lists.freedesktop.org/archives/intel-gfx/2015-July/071080.html
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
(cherry picked from commit af768922cafa3eb3e78a2fdfee90380a74c79460)
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Conflicts:
src/mesa/drivers/dri/i965/brw_defines.h
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index b53e186..30867a6 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -2471,12 +2471,13 @@ enum brw_wm_barycentric_interp_mode {
#define BDW_MOCS_WT 0x58
#define BDW_MOCS_PTE 0x18
-/* Skylake: MOCS is now an index into an array of 64 different configurable
- * cache settings. We still use only either write-back or write-through; and
- * rely on the documented default values.
+/* Skylake: MOCS is now an index into an array of 62 different caching
+ * configurations programmed by the kernel.
*/
-#define SKL_MOCS_WB 9
-#define SKL_MOCS_WT 5
+/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
+#define SKL_MOCS_WB (2 << 1)
+/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
+#define SKL_MOCS_PTE (1 << 1)
#define MEDIA_VFE_STATE 0x7000
/* GEN7 DW2, GEN8+ DW3 */
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 672fc70..c7ea01a 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -349,8 +349,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1));
GLenum gl_target =
rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
- /* FINISHME: Use PTE MOCS on Skylake. */
- uint32_t mocs = brw->gen >= 9 ? SKL_MOCS_WT : BDW_MOCS_PTE;
+ const uint32_t mocs = brw->gen >= 9 ? SKL_MOCS_PTE : BDW_MOCS_PTE;
intel_miptree_used_for_rendering(mt);
commit 8132c7ac41f07857368aef25cbc4a26979784ba4
Author: Brian Paul <brianp@vmware.com>
Date: Wed Jul 15 06:15:06 2015 -0600
osmesa: fix OSMesaPixelsStore typo
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91337
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 141e1eb29fe80ad341e718147a1277cc3b1b9c11)
diff --git a/src/gallium/state_trackers/osmesa/osmesa.c b/src/gallium/state_trackers/osmesa/osmesa.c
index 2d5d096..96b8358 100644
--- a/src/gallium/state_trackers/osmesa/osmesa.c
+++ b/src/gallium/state_trackers/osmesa/osmesa.c
@@ -886,7 +886,7 @@ static struct name_function functions[] = {
{ "OSMesaDestroyContext", (OSMESAproc) OSMesaDestroyContext },
{ "OSMesaMakeCurrent", (OSMESAproc) OSMesaMakeCurrent },
{ "OSMesaGetCurrentContext", (OSMESAproc) OSMesaGetCurrentContext },
- { "OSMesaPixelsStore", (OSMESAproc) OSMesaPixelStore },
+ { "OSMesaPixelStore", (OSMESAproc) OSMesaPixelStore },
{ "OSMesaGetIntegerv", (OSMESAproc) OSMesaGetIntegerv },
{ "OSMesaGetDepthBuffer", (OSMESAproc) OSMesaGetDepthBuffer },
{ "OSMesaGetColorBuffer", (OSMESAproc) OSMesaGetColorBuffer },
diff --git a/src/mesa/drivers/osmesa/osmesa.c b/src/mesa/drivers/osmesa/osmesa.c
index 022523e..5c7dcac 100644
--- a/src/mesa/drivers/osmesa/osmesa.c
+++ b/src/mesa/drivers/osmesa/osmesa.c
@@ -1124,7 +1124,7 @@ static struct name_function functions[] = {
{ "OSMesaDestroyContext", (OSMESAproc) OSMesaDestroyContext },
{ "OSMesaMakeCurrent", (OSMESAproc) OSMesaMakeCurrent },
{ "OSMesaGetCurrentContext", (OSMESAproc) OSMesaGetCurrentContext },
- { "OSMesaPixelsStore", (OSMESAproc) OSMesaPixelStore },
+ { "OSMesaPixelStore", (OSMESAproc) OSMesaPixelStore },
{ "OSMesaGetIntegerv", (OSMESAproc) OSMesaGetIntegerv },
{ "OSMesaGetDepthBuffer", (OSMESAproc) OSMesaGetDepthBuffer },
{ "OSMesaGetColorBuffer", (OSMESAproc) OSMesaGetColorBuffer },
commit da8bc1673936b9c9ba83c3d60fd03ce383bc8e85
Author: Emil Velikov <emil.l.velikov@gmail.com>
Date: Fri Jul 10 21:27:13 2015 +0100
auxiliary/vl: use the correct screen index
Inspired (copied) from Marek's commit for egl/x11
commit 0b56e23e7f3(egl/dri2: use the correct screen index)
v2: Fix copy/pasta errors.
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 7a50bf6c7f7729f5eee3ddf7aa9b38a81873f2c6)
diff --git a/src/gallium/auxiliary/vl/vl_winsys_dri.c b/src/gallium/auxiliary/vl/vl_winsys_dri.c
index 7e61b88..1e6613c 100644
--- a/src/gallium/auxiliary/vl/vl_winsys_dri.c
+++ b/src/gallium/auxiliary/vl/vl_winsys_dri.c
@@ -293,6 +293,16 @@ vl_screen_get_private(struct vl_screen *vscreen)
return vscreen;
}
+static xcb_screen_t *
+get_xcb_screen(xcb_screen_iterator_t iter, int screen)
+{
+ for (; iter.rem; --screen, xcb_screen_next(&iter))
+ if (screen == 0)
+ return iter.data;
+
+ return NULL;
+}
+
struct vl_screen*
vl_screen_create(Display *display, int screen)
{
@@ -334,8 +344,7 @@ vl_screen_create(Display *display, int screen)
goto free_query;
s = xcb_setup_roots_iterator(xcb_get_setup(scrn->conn));
- while (screen--)
- xcb_screen_next(&s);
+
driverType = XCB_DRI2_DRIVER_TYPE_DRI;
#ifdef DRI2DriverPrimeShift
{
@@ -351,7 +360,7 @@ vl_screen_create(Display *display, int screen)
}
#endif
- connect_cookie = xcb_dri2_connect_unchecked(scrn->conn, s.data->root, driverType);
+ connect_cookie = xcb_dri2_connect_unchecked(scrn->conn, get_xcb_screen(s, screen)->root, driverType);
connect = xcb_dri2_connect_reply(scrn->conn, connect_cookie, NULL);
if (connect == NULL || connect->driver_name_length + connect->device_name_length == 0)
goto free_connect;
@@ -370,7 +379,7 @@ vl_screen_create(Display *display, int screen)
if (drmGetMagic(fd, &magic))
goto free_connect;
- authenticate_cookie = xcb_dri2_authenticate_unchecked(scrn->conn, s.data->root, magic);
+ authenticate_cookie = xcb_dri2_authenticate_unchecked(scrn->conn, get_xcb_screen(s, screen)->root, magic);
authenticate = xcb_dri2_authenticate_reply(scrn->conn, authenticate_cookie, NULL);
if (authenticate == NULL || !authenticate->authenticated)
commit 6012eeca0b44240b5ddc40650266eeaeb076d6fa
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Fri Jul 10 16:42:18 2015 -0400
nv50, nvc0: enable at least one color RT if alphatest is enabled
Fixes the following piglits:
fbo-alphatest-nocolor
fbo-alphatest-nocolor-ff
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 1bfa25e88d21f95b9e176232bb091af77c294578)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
index 116bf4b..293f980 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
@@ -296,6 +296,23 @@ nv50_check_program_ucps(struct nv50_context *nv50,
nv50_fp_linkage_validate(nv50);
}
+/* alpha test is disabled if there are no color RTs, so make sure we have at
+ * least one if alpha test is enabled. Note that this must run after
+ * nv50_validate_fb, otherwise that will override the RT count setting.
+ */
+static void
+nv50_validate_derived_2(struct nv50_context *nv50)
+{
+ struct nouveau_pushbuf *push = nv50->base.pushbuf;
+
+ if (nv50->zsa && nv50->zsa->pipe.alpha.enabled &&
+ nv50->framebuffer.nr_cbufs == 0) {
+ nv50_fb_set_null_rt(push, 0);
+ BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
+ PUSH_DATA (push, (076543210 << 4) | 1);
+ }
+}
+
static void
nv50_validate_clip(struct nv50_context *nv50)
{
@@ -456,6 +473,7 @@ static struct state_validate {
{ nv50_gp_linkage_validate, NV50_NEW_GMTYPROG | NV50_NEW_VERTPROG },
{ nv50_validate_derived_rs, NV50_NEW_FRAGPROG | NV50_NEW_RASTERIZER |
NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG },
+ { nv50_validate_derived_2, NV50_NEW_ZSA | NV50_NEW_FRAMEBUFFER },
{ nv50_validate_clip, NV50_NEW_CLIP | NV50_NEW_RASTERIZER |
NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG },
{ nv50_constbufs_validate, NV50_NEW_CONSTBUF },
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c b/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
index d3ad81d..4ffcbd0 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
@@ -535,6 +535,23 @@ nvc0_validate_derived_1(struct nvc0_context *nvc0)
}
}
+/* alpha test is disabled if there are no color RTs, so make sure we have at
+ * least one if alpha test is enabled. Note that this must run after
+ * nvc0_validate_fb, otherwise that will override the RT count setting.
+ */
+static void
+nvc0_validate_derived_2(struct nvc0_context *nvc0)
+{
+ struct nouveau_pushbuf *push = nvc0->base.pushbuf;
+
+ if (nvc0->zsa && nvc0->zsa->pipe.alpha.enabled &&
+ nvc0->framebuffer.nr_cbufs == 0) {
+ nvc0_fb_set_null_rt(push, 0);
+ BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
+ PUSH_DATA (push, (076543210 << 4) | 1);
+ }
+}
+
static void
nvc0_switch_pipe_context(struct nvc0_context *ctx_to)
{
@@ -597,6 +614,7 @@ static struct state_validate {
{ nvc0_fragprog_validate, NVC0_NEW_FRAGPROG },
{ nvc0_validate_derived_1, NVC0_NEW_FRAGPROG | NVC0_NEW_ZSA |
NVC0_NEW_RASTERIZER },
+ { nvc0_validate_derived_2, NVC0_NEW_ZSA | NVC0_NEW_FRAMEBUFFER },
{ nvc0_validate_clip, NVC0_NEW_CLIP | NVC0_NEW_RASTERIZER |
NVC0_NEW_VERTPROG |
NVC0_NEW_TEVLPROG |
commit 9c7f5947058b17d2fd117e475a0395a6a1f745af
Author: Chad Versace <chad.versace@intel.com>
Date: Thu Jul 9 18:46:21 2015 -0700
mesa: Fix generation of git_sha1.h.tmp for gitlinks
Don't assume that $(top_srcdir)/.git is a directory. It may be a
gitlink file [1] if $(top_srcdir) is a submodule checkout or a linked
worktree [2].
[1] A "gitlink" is a text file that specifies the real location of
the gitdir.
[2] Linked worktrees are a new feature in Git 2.5.
Cc: "10.6, 10.5" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit 75784243df1f5bb0652fb243b37d69f36d493a86)
diff --git a/src/mesa/Makefile.am b/src/mesa/Makefile.am
index 71794b5..4ba5b2f 100644
--- a/src/mesa/Makefile.am
+++ b/src/mesa/Makefile.am
@@ -40,8 +40,11 @@ gl_HEADERS = $(top_srcdir)/include/GL/*.h
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