mesa: Changes to 'ubuntu+1'
debian/patches/i965-define-i915-param-revision.diff | 27 ---
debian/patches/i965-refactor-simd16-to-2xsimd8-checks.diff | 72 ---------
debian/patches/i965-store-the-gpu-revision.diff | 80 ----------
debian/patches/skl-break-down-simd16-3-source-instructions.diff | 34 ----
4 files changed, 213 deletions(-)
New commits:
commit 223af6b1ca12cb0c761a98767932d7cc7cc9b8cb
Author: Timo Aaltonen <tjaalton@debian.org>
Date: Tue Jul 7 01:29:37 2015 +0300
actually remove the backported patches too
diff --git a/debian/patches/i965-define-i915-param-revision.diff b/debian/patches/i965-define-i915-param-revision.diff
deleted file mode 100644
index 1d0c831..0000000
--- a/debian/patches/i965-define-i915-param-revision.diff
+++ /dev/null
@@ -1,27 +0,0 @@
-commit 484f9f4fcd53fcaa768e63934a5f74346bfb46a9
-Author: Dave Airlie <airlied@redhat.com>
-Date: Mon Mar 23 09:54:52 2015 +1000
-
- i965: define I915_PARAM_REVISION
-
- we are broken against the libdrm 2.4.60 minimum specified,
- so fix it for now.
-
- Signed-off-by: Dave Airlie <airlied@redhat.com>
-
-diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
-index 0d3af2c..a39443a 100644
---- a/src/mesa/drivers/dri/i965/brw_context.c
-+++ b/src/mesa/drivers/dri/i965/brw_context.c
-@@ -658,6 +658,11 @@ brw_process_driconf_options(struct brw_context *brw)
- driQueryOptionb(options, "allow_glsl_extension_directive_midshader");
- }
-
-+/* drop when libdrm 2.4.61 is released */
-+#ifndef I915_PARAM_REVISION
-+#define I915_PARAM_REVISION 32
-+#endif
-+
- static int
- brw_get_revision(int fd)
- {
diff --git a/debian/patches/i965-refactor-simd16-to-2xsimd8-checks.diff b/debian/patches/i965-refactor-simd16-to-2xsimd8-checks.diff
deleted file mode 100644
index c595ea2..0000000
--- a/debian/patches/i965-refactor-simd16-to-2xsimd8-checks.diff
+++ /dev/null
@@ -1,72 +0,0 @@
-commit bc4b18d2977a94a6fb513bf5955236a0e92298ca
-Author: Neil Roberts <neil@linux.intel.com>
-Date: Thu Mar 19 18:18:49 2015 +0000
-
- i965: Refactor SIMD16-to-2xSIMD8 checks.
-
- The places that were checking whether 3-source instructions are
- supported have now been combined into a small helper function. This
- will be used in the next patch to add an additonal restriction.
-
- Based on a patch by Kenneth Graunke.
-
- Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
- Reviewed-by: Matt Turner <mattst88@gmail.com>
-
-diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
-index 05a2db4..6eebee1 100644
---- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
-+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
-@@ -1553,6 +1553,15 @@ fs_generator::enable_debug(const char *shader_name)
- this->shader_name = shader_name;
- }
-
-+/**
-+ * Some hardware doesn't support SIMD16 instructions with 3 sources.
-+ */
-+static bool
-+brw_supports_simd16_3src(const struct brw_context *brw)
-+{
-+ return brw->is_haswell || brw->gen >= 8;
-+}
-+
- int
- fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
- {
-@@ -1646,7 +1655,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
- case BRW_OPCODE_MAD:
- assert(brw->gen >= 6);
- brw_set_default_access_mode(p, BRW_ALIGN_16);
-- if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
-+ if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
- brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
- brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
- brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
-@@ -1667,7 +1676,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
- case BRW_OPCODE_LRP:
- assert(brw->gen >= 6);
- brw_set_default_access_mode(p, BRW_ALIGN_16);
-- if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
-+ if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
- brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
- brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
- brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
-@@ -1804,7 +1813,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
- case BRW_OPCODE_BFE:
- assert(brw->gen >= 7);
- brw_set_default_access_mode(p, BRW_ALIGN_16);
-- if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
-+ if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
- brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
- brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
- brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
-@@ -1844,7 +1853,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
- * Otherwise we would be able to emit compressed instructions like we
- * do for the other three-source instructions.
- */
-- if (dispatch_width == 16 && brw->gen < 8) {
-+ if (dispatch_width == 16 &&
-+ (brw->is_haswell || !brw_supports_simd16_3src(brw))) {
- brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
- brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
- brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
diff --git a/debian/patches/i965-store-the-gpu-revision.diff b/debian/patches/i965-store-the-gpu-revision.diff
deleted file mode 100644
index 94d8554..0000000
--- a/debian/patches/i965-store-the-gpu-revision.diff
+++ /dev/null
@@ -1,80 +0,0 @@
-commit c02c4b567ce001f6605c46e71e089692b837bf26
-Author: Neil Roberts <neil@linux.intel.com>
-Date: Wed Mar 4 14:13:40 2015 +0000
-
- i965: Store the GPU revision number in brw_context
-
- brwContextInit now queries the GPU revision number via a new parameter
- for DRM_I915_GETPARAM. This new parameter requires a kernel patch and
- a patch to libdrm. If the kernel doesn't support it then it will
- continue but set the revision number to -1. The intention is to use
- this to implement workarounds that are only needed on certain
- steppings of the GPU.
-
- Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
-
-diff --git a/configure.ac b/configure.ac
-index 8c90b41..d864350 100644
---- a/configure.ac
-+++ b/configure.ac
-@@ -61,7 +61,7 @@ AC_SUBST([OSMESA_VERSION])
- dnl Versions for external dependencies
- LIBDRM_REQUIRED=2.4.38
- LIBDRM_RADEON_REQUIRED=2.4.56
--LIBDRM_INTEL_REQUIRED=2.4.52
-+LIBDRM_INTEL_REQUIRED=2.4.60
- LIBDRM_NVVIEUX_REQUIRED=2.4.33
- LIBDRM_NOUVEAU_REQUIRED="2.4.33 libdrm >= 2.4.41"
- LIBDRM_FREEDRENO_REQUIRED=2.4.57
-diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
-index 88685cd..0d3af2c 100644
---- a/src/mesa/drivers/dri/i965/brw_context.c
-+++ b/src/mesa/drivers/dri/i965/brw_context.c
-@@ -658,6 +658,24 @@ brw_process_driconf_options(struct brw_context *brw)
- driQueryOptionb(options, "allow_glsl_extension_directive_midshader");
- }
-
-+static int
-+brw_get_revision(int fd)
-+{
-+ struct drm_i915_getparam gp;
-+ int revision;
-+ int ret;
-+
-+ memset(&gp, 0, sizeof(gp));
-+ gp.param = I915_PARAM_REVISION;
-+ gp.value = &revision;
-+
-+ ret = drmCommandWriteRead(fd, DRM_I915_GETPARAM, &gp, sizeof(gp));
-+ if (ret)
-+ revision = -1;
-+
-+ return revision;
-+}
-+
- GLboolean
- brwCreateContext(gl_api api,
- const struct gl_config *mesaVis,
-@@ -716,6 +734,7 @@ brwCreateContext(gl_api api,
- brw->has_negative_rhw_bug = devinfo->has_negative_rhw_bug;
- brw->needs_unlit_centroid_workaround =
- devinfo->needs_unlit_centroid_workaround;
-+ brw->revision = brw_get_revision(sPriv->fd);
-
- brw->must_use_separate_stencil = screen->hw_must_use_separate_stencil;
- brw->has_swizzling = screen->hw_has_swizzling;
-diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
-index 8b29e2a..e025011 100644
---- a/src/mesa/drivers/dri/i965/brw_context.h
-+++ b/src/mesa/drivers/dri/i965/brw_context.h
-@@ -1076,6 +1076,10 @@ struct brw_context
-
- int gen;
- int gt;
-+ /* GT revision. This will be -1 if the revision couldn't be determined (eg,
-+ * if the kernel doesn't support the query).
-+ */
-+ int revision;
-
- bool is_g4x;
- bool is_baytrail;
diff --git a/debian/patches/skl-break-down-simd16-3-source-instructions.diff b/debian/patches/skl-break-down-simd16-3-source-instructions.diff
deleted file mode 100644
index 527230d..0000000
--- a/debian/patches/skl-break-down-simd16-3-source-instructions.diff
+++ /dev/null
@@ -1,34 +0,0 @@
-commit 706b916960c898cfc24110f14fa4def84caaba93
-Author: Kenneth Graunke <kenneth@whitecape.org>
-Date: Wed Mar 4 12:53:45 2015 -0800
-
- i965/skl: Break down SIMD16 3-source instructions when required.
-
- Several steppings of Skylake fail when using SIMD16 with 3-source
- instructions (such as MAD).
-
- This implements WaDisableSIMD16On3SrcInstr and fixes ~190 Piglit
- tests.
-
- Based on a patch by Neil Roberts.
-
- Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
- Reviewed-by: Neil Roberts <neil@linux.intel.com>
-
-diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
-index 6eebee1..3aa5c3c 100644
---- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
-+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
-@@ -1559,6 +1559,12 @@ fs_generator::enable_debug(const char *shader_name)
- static bool
- brw_supports_simd16_3src(const struct brw_context *brw)
- {
-+ /* WaDisableSIMD16On3SrcInstr: 3-source instructions don't work in SIMD16
-+ * on a few steppings of Skylake.
-+ */
-+ if (brw->gen == 9)
-+ return brw->revision != 2 && brw->revision != 3 && brw->revision != -1;
-+
- return brw->is_haswell || brw->gen >= 8;
- }
-
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