xserver-xorg-video-ati: Changes to 'debian-unstable'
ChangeLog | 515 ++++++++++++++++++++++++++++++++++++
configure.ac | 14
debian/changelog | 11
debian/control | 2
man/radeon.man | 20 +
src/ati_pciids_gen.h | 26 +
src/drmmode_display.c | 161 +++++++++--
src/drmmode_display.h | 1
src/evergreen_accel.c | 190 +++++++++++--
src/evergreen_exa.c | 45 ++-
src/evergreen_state.h | 7
src/evergreen_textured_videofuncs.c | 7
src/pcidb/ati_pciids.csv | 26 +
src/r600_exa.c | 86 +++---
src/r600_state.h | 6
src/r600_textured_videofuncs.c | 20 +
src/r6xx_accel.c | 75 +++--
src/radeon.h | 21 +
src/radeon_chipinfo_gen.h | 26 +
src/radeon_chipset_gen.h | 26 +
src/radeon_commonfuncs.c | 17 -
src/radeon_crtc.c | 27 +
src/radeon_dri2.c | 162 +++++------
src/radeon_driver.c | 71 ++--
src/radeon_drm.h | 23 +
src/radeon_exa.c | 87 +++++-
src/radeon_kms.c | 84 +++++
src/radeon_output.c | 4
src/radeon_pci_chipset_gen.h | 26 +
src/radeon_pci_device_match_gen.h | 26 +
src/radeon_probe.h | 7
src/radeon_textured_video.c | 17 +
src/radeon_textured_videofuncs.c | 68 ++--
33 files changed, 1602 insertions(+), 302 deletions(-)
New commits:
commit 9878dca8e56c95a8fcda0255c7f92d0b87d815b5
Author: Cyril Brulebois <kibi@debian.org>
Date: Mon Apr 2 20:21:38 2012 +0000
Upload to unstable.
diff --git a/debian/changelog b/debian/changelog
index 87a84b9..99b4bb5 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-xserver-xorg-video-ati (1:6.14.4-1) UNRELEASED; urgency=low
+xserver-xorg-video-ati (1:6.14.4-1) unstable; urgency=low
* New upstream release:
- Add support for Trinity APUs.
@@ -7,7 +7,7 @@ xserver-xorg-video-ati (1:6.14.4-1) UNRELEASED; urgency=low
- Lots of bug fixes.
* Bump libdrm-dev build-dep.
- -- Cyril Brulebois <kibi@debian.org> Mon, 02 Apr 2012 20:10:07 +0000
+ -- Cyril Brulebois <kibi@debian.org> Mon, 02 Apr 2012 20:21:35 +0000
xserver-xorg-video-ati (1:6.14.3-2) unstable; urgency=low
commit 2a66a8ba46529b3f789652d376b95b038dc8a96b
Author: Cyril Brulebois <kibi@debian.org>
Date: Mon Apr 2 20:21:17 2012 +0000
Document new upstream release thanks to the announce.
diff --git a/debian/changelog b/debian/changelog
index 36286a2..87a84b9 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,6 +1,10 @@
xserver-xorg-video-ati (1:6.14.4-1) UNRELEASED; urgency=low
- * New upstream release.
+ * New upstream release:
+ - Add support for Trinity APUs.
+ - 2D tiling support on R6xx+ asics.
+ - KMS tiling support for r1xx-r2xx.
+ - Lots of bug fixes.
* Bump libdrm-dev build-dep.
-- Cyril Brulebois <kibi@debian.org> Mon, 02 Apr 2012 20:10:07 +0000
commit 41098d50f49b25ba8d53b190599a2e3f2b42b312
Author: Cyril Brulebois <kibi@debian.org>
Date: Mon Apr 2 20:20:33 2012 +0000
Bump libdrm-dev build-dep.
diff --git a/debian/changelog b/debian/changelog
index 913b223..36286a2 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,6 +1,7 @@
xserver-xorg-video-ati (1:6.14.4-1) UNRELEASED; urgency=low
* New upstream release.
+ * Bump libdrm-dev build-dep.
-- Cyril Brulebois <kibi@debian.org> Mon, 02 Apr 2012 20:10:07 +0000
diff --git a/debian/control b/debian/control
index 6d428a6..455402a 100644
--- a/debian/control
+++ b/debian/control
@@ -17,7 +17,7 @@ Build-Depends:
x11proto-fonts-dev,
x11proto-randr-dev (>= 1.2),
x11proto-render-dev,
- libdrm-dev (>= 2.4.17) [!hurd-i386],
+ libdrm-dev (>= 2.4.33) [!hurd-i386],
x11proto-dri2-dev,
x11proto-xf86dri-dev,
libudev-dev [linux-any],
commit bfac7a1890fa583b3d8db0966fac6dbce99f4e78
Author: Cyril Brulebois <kibi@debian.org>
Date: Mon Apr 2 20:10:17 2012 +0000
Bump changelogs.
diff --git a/ChangeLog b/ChangeLog
index 7f195e0..db00375 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,518 @@
+commit 9425c50e93903fb64d9e569cfdc1e2c35d16ce25
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Thu Mar 29 00:19:12 2012 -0400
+
+ configure: bump version for release
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit dc18d771713ecd893c7d5833da6e0661093161dc
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Wed Mar 28 17:32:53 2012 -0400
+
+ configure: bump libdrm requirement for TN support
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit 03535904a3e1542b3924d0a062c4b022ca196888
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Tue Mar 27 09:48:28 2012 -0400
+
+ radeon: man page updates
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit 6ed191c33caa33c12c2c6dafcba3a5ab1bf4a02f
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Tue Mar 20 19:57:53 2012 -0400
+
+ radeon/kms: add TN pci ids
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit 55d65fcf33eb383e3fbc7a1d469ab68a70a7ab37
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Tue Mar 20 19:54:57 2012 -0400
+
+ radeon/kms: add support for TN (trinity) APUs
+
+ - KMS only
+ - Includes full EXA/Xv support
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit b5cf9bd693cf4090956add4c33c4fae9c3069a03
+Author: Marek Olšák <maraeo@gmail.com>
+Date: Wed Mar 7 11:01:40 2012 -0500
+
+ r6xx: initialize SX_MISC
+
+ If Mesa set it to 1, the DDX would not render anything = the monitor would
+ basically freeze.
+
+ agd5f: update emit count as well.
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit 355dc4295912c153f5333421594fa90aa119a056
+Author: Michel Dänzer <michel.daenzer@amd.com>
+Date: Tue Mar 6 15:52:40 2012 +0100
+
+ DRI2: Unreference buffers immediately when event wait info is invalidated.
+
+ Deferring this could result in trying to unreference buffers from a previous
+ server generation, i.e. accessing freed memory.
+
+ Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
+ Tested-by: Christian König <Christian.koenig@amd.com>
+
+commit fe51469b2e02e4d565050bab077985270fb58a9b
+Author: Michel Dänzer <michel.daenzer@amd.com>
+Date: Tue Mar 6 15:52:40 2012 +0100
+
+ Re-register DRM FD wakeup handler for each server generation.
+
+ Fixes hang when trying to use DRI2 swap scheduling after a server reset.
+
+ Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
+ Tested-by: Christian König <Christian.koenig@amd.com>
+
+commit 878454ae8d8e96dd27a19d0b30940d014c4cd7e2
+Author: Hans Verkuil <hverkuil@xs4all.nl>
+Date: Fri Feb 24 09:35:39 2012 -0500
+
+ Fix ConnectorTable crash in radeon_output.c
+
+ The sam440ep PPC board requires a ConnectorTable xorg.conf option, but putting
+ in that option causes the radeon driver to crash. I finally traced it to a
+ copy-and-paste bug in radeon_output.c as a result of a major rework in commit
+ 82f12e5a40c1fbcb91910a0f8b725c34fff02aae.
+
+ The actual crash occurred in RADEONPrintPortMap().
+
+ Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit 688c8a54a00b01e73a11970ad2abe858f8c7c5c4
+Author: Roland Scheidegger <rscheidegger_lists@hispeed.ch>
+Date: Sat Feb 18 21:12:34 2012 +0100
+
+ radeon: avoid rounding errors in texture coords for textured xv
+
+ make sure the division is done with floats, otherwise the coordinate
+ can be wrong up to 1 texel.
+ Particularly visible with clipping and small source scaled up (since one
+ texel can be a shift of several pixels) but could be seen even unscaled.
+ Should provide more accurate coords without clipping too depending on the
+ scale factor probably.
+ Changed for r100-r600, though only tested on r300.
+
+commit 2778b56252124ef6f636a493d2e1457b43911c37
+Author: Jerome Glisse <jglisse@redhat.com>
+Date: Mon Feb 13 20:42:57 2012 -0500
+
+ radeon: r6xx-eg use linear general when using scratch bo
+
+ In path where we need to use scratch bo as temporary area,
+ consider it as linear buffer. Not linear aligned. Fix some
+ case such as in bugs:
+
+ https://bugs.freedesktop.org/show_bug.cgi?id=45827
+
+ Signed-off-by: Jerome Glisse <jglisse@redhat.com>
+
+commit c66ae235700f5efe64eb168327551b8f1d153c9c
+Author: Michel Dänzer <michel.daenzer@amd.com>
+Date: Mon Feb 13 10:43:58 2012 +0100
+
+ Handle new xorg_list API.
+
+ Fixes https://bugs.freedesktop.org/show_bug.cgi?id=45937
+
+ Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
+
+commit 7ff277e22c629308915307bbee96eb25ff77f8b9
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Fri Feb 10 13:04:59 2012 -0500
+
+ radeon: fix crash in drmmode_create_bo_pixmap()
+
+ Only init surface on r6xx+. Return NULL rather than
+ FALSE.
+
+ Fixes:
+ https://bugs.freedesktop.org/show_bug.cgi?id=45829
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit 60b949f34df5db05e0e102cc3daa33469aa50cfc
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Fri Feb 10 13:11:26 2012 -0500
+
+ radeon/kms: reusing fd message is not an error
+
+ It's standard behavior.
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit e20284409937d784847339b5d466a95012d85940
+Author: Michel Dänzer <michel.daenzer@amd.com>
+Date: Fri Feb 3 12:21:59 2012 +0100
+
+ EXA/r6xx+: Only set write domain or read domains, not both. (Bug #43893)
+
+ Avoids an accounting bug in libdrm_radeon 2.4.31 or older.
+
+ See https://bugs.freedesktop.org/show_bug.cgi?id=43893
+
+ Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
+
+commit 5a7f64c5170ca424c9dca739662018e30df13413
+Author: Michel Dänzer <michel.daenzer@amd.com>
+Date: Wed Feb 8 11:35:35 2012 +0100
+
+ Fix UMS build failure.
+
+ And some UMS specific warnings.
+
+ Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
+
+commit 87f776b966f4200c97a989536d4b71822ae4c0b3
+Author: Michel Dänzer <michel.daenzer@amd.com>
+Date: Wed Feb 8 11:10:27 2012 +0100
+
+ Remove unused local variable 'height'.
+
+ Pointed out by gcc -Wunused-variable.
+
+ Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
+
+commit f63262e2f112a348c45f0dcecd891c8b6d9c5ee8
+Author: Michel Dänzer <michel.daenzer@amd.com>
+Date: Wed Feb 8 10:28:45 2012 +0100
+
+ evergreen: Initialize source surface member for textured video.
+
+ Fixes crash reported by Ole Salscheider on IRC.
+
+ Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
+
+commit c8f104d38870f14049402bbc14f662c151caeeef
+Author: Jerome Glisse <jglisse@redhat.com>
+Date: Tue Feb 7 15:04:37 2012 -0500
+
+ radeon: fix tiling for weird resolution
+
+ Should also fix xv for some case.
+
+ Signed-off-by: Jerome Glisse <jglisse@redhat.com>
+
+commit 615033f2b5e3817e335e9d022fc9fdcf8ac8b11a
+Author: Jerome Glisse <jglisse@redhat.com>
+Date: Tue Dec 13 11:08:19 2011 -0500
+
+ r600-evergreen: use common surface allocator for tiling v11
+
+ Use libdrm common surface code so mesa,ddx have same idea
+ about tiling surface and what their pitch should be and
+ the alignment constraint.
+
+ v2 fix remaining issue add new option to conditionaly enable
+ v3 fix fbcon copy and r600 exa copy path
+ v4 fix non tiled path 2D tiling on GPU >= R600, set it to false
+ as default
+ v5 adapt to pixel/element size split of libdrm/radeon
+ v6 update to properly handle falling back to 1d tiled
+ v6 final fix to tile split value on evergreen and newer
+ v7 fix default array mode on r6xx, fix height alignment issue
+ on evergreen
+ v8 fix tile split value
+ v9 add stencil tile split support, simplify dri2 for stencil
+ with evergreen
+ v10 Try to fix xv path regarding tiling. Adapt to libdrm API
+ change. Try to fix case where there is no surface which
+ means non tiled bo.
+ v11 check for proper libdrm
+
+ Signed-off-by: Jerome Glisse <jglisse@redhat.com>
+
+commit 36c190671081967bac6fff48aaf66d67b639a48c
+Author: Michel Dänzer <michel.daenzer@amd.com>
+Date: Wed Feb 1 13:21:02 2012 +0100
+
+ Fix vline range calculations.
+
+ The range passed in is in pixmap coordinates, so the CRTC offset needs to be
+ added to the clamping limits and subtracted from the clamped range for
+ pre-AVIVO display engines.
+
+ Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
+ Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit bb0e1531ac6949d38025d7dcb19234fee33b2acf
+Author: Michel Dänzer <michel.daenzer@amd.com>
+Date: Wed Feb 1 13:07:11 2012 +0100
+
+ Check for empty vline ranges after clamping.
+
+ The clamping could turn a previously non-empty range into an empty one.
+
+ Also, start == stop means the range is empty.
+
+ Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
+ Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit 13b3aed4ef9afbcbaea1dcf0ed1acb162b240a3f
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Tue Jan 10 09:35:09 2012 -0500
+
+ EXA/r6xx+: fix rop setting for overlapping copies
+
+ Need to use GXCopy for the src to temp copy, then
+ the original rop for the temp to dest copy.
+
+ Noticed by: Frank Huang
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit eb6d769a087b2ed5952f477fc3f0b0625810a287
+Author: Egbert Eich <eich@suse.de>
+Date: Tue Nov 15 18:50:56 2011 +0100
+
+ DPMS: Split non-modeset CRTC DPMS function.
+
+ RADEONRestore() calls crtc->funcs->dpms() after most of the mode setting
+ subsystems have been restored. This function enables the CRTCs but does
+ more: it calls DRM pre- and post-modeset ioctls and sets up the palettes
+ (LUTs).
+ None of these two things are needed. Accessing the palette registers after
+ restoring the PLLs can even lead to lockups.
+ Thus the CRTC DPMS function is split into two parts: one that just enables
+ /disables the CRTC and one which wraps this function and does the rest.
+ Now the inner function can be called directly from RADEONRestore() as
+ there is no need to go thru the RandR hooks in this function while the
+ RandR hook uses the wrappering function so the full functionality is
+ preserved from an RandR point of view.
+
+ Signed-off-by: Egbert Eich <eich@freedesktop.org>
+ Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit ac51e331895b216d288bc7bd108a38b362214668
+Author: Egbert Eich <eich@suse.de>
+Date: Mon Nov 14 19:10:01 2011 +0100
+
+ UMS: Fix lockups in palette save/restore on pre-AVIVO chips.
+
+ The reintroduction of palette save/restore in 5efdf514 causes some
+ pre-AVIVO chips to lock up. An investigation revealed that accessing
+ palette registers when the associated PLL is not running is causing
+ this. With UMS the PLL setup that is saved has been done by the BIOS
+ typically.
+ A similar issue was observed when VGA palette save/restore had
+ been reinitroduced with 80eee856:
+ http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=480312
+ and has been worked around for Linux without further investigation
+ by 87e66ce7.
+ To fix the issue we now
+ a. introduce 'on-demand' palette saving (ie the palette is
+ saved before it is first altered). This guarantees that
+ the palette register are only associated when the associated
+ CRTC is active and thus the PLLs are powered up and running.
+ b. move palette restore before PLL restore.
+ c. eliminate generic VGA palette save/restore which seems to be
+ unneeded when the palette is restored natively.
+ It is believed that this caused the behavior described in
+ https://bugs.freedesktop.org/show_bug.cgi?id=18407#c27
+
+ Signed-off-by: Egbert Eich <eich@freedesktop.org>
+ Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit 0a8d04eeac95f4db9d03ee31070bd825a7feb0b2
+Author: Matthieu Herrb <matthieu.herrb@laas.fr>
+Date: Sun Jan 1 18:27:54 2012 +0100
+
+ Update for new vgaHW API.
+
+ Signed-off-by: Matthieu Herrb <matthieu.herrb@laas.fr>
+ Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit ae45d7e6d8e6844cd4586c9ee97c21b257fa788f
+Author: Michel Dänzer <michel.daenzer@amd.com>
+Date: Wed Dec 28 11:48:36 2011 +0100
+
+ DRI2: Can't use page flipping for pixmaps. (bug #42913)
+
+ Fixes https://bugs.freedesktop.org/show_bug.cgi?id=42913 .
+
+ Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
+
+commit aacbd629b02cbee3f9e6a0ee452b4e3f21376bd3
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon Dec 12 09:32:30 2011 -0500
+
+ radeon: add some new pci ids
+
+ fixes:
+ https://bugs.freedesktop.org/show_bug.cgi?id=43739
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit bc54e415e2fd344939c5c788ea0686133a7e2c69
+Author: Dave Airlie <airlied@redhat.com>
+Date: Tue Dec 6 15:47:45 2011 +0000
+
+ radeon: add original radeon to always tiled.
+
+ and actually enable it for M7, previous commit only did one function.
+
+ Signed-off-by: Dave Airlie <airlied@redhat.com>
+
+commit ba46c7b0cf72d157748981eb3224d5eefb6200aa
+Author: Dave Airlie <airlied@redhat.com>
+Date: Tue Dec 6 13:42:49 2011 +0000
+
+ radeon: refine always tiled depth check
+
+ So it appears the M7 family always tiles its depth buffer also.
+
+ Signed-off-by: Dave Airlie <airlied@redhat.com>
+
+commit 98b2d5fe1722a43c4bbe7711ed7180a3fb65305f
+Author: Dave Airlie <airlied@redhat.com>
+Date: Mon Dec 5 18:44:28 2011 +0000
+
+ radeon: r200 depth buffers are always tiled
+
+ When we do the allocations we need to make sure the always tiled
+ nature is taken into account.
+
+ Signed-off-by: Dave Airlie <airlied@redhat.com>
+
+commit 7dcefc69d9fbceae27cd03083c815e01a19b527e
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon Dec 5 09:21:48 2011 -0500
+
+ Xv: Evergreen+ asics support 16k surfaces
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit 72e386d42516e7cd3c2cbf2fffc9174cd3ec8451
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed Nov 30 19:38:35 2011 -0500
+
+ radeon: add some new pci ids
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit 3853c3020d05175ae180b9a188dec7c425bdd0b8
+Author: Dave Airlie <airlied@redhat.com>
+Date: Mon Nov 28 18:38:30 2011 +0000
+
+ fixup xinerama since 9151f3b1c2ebcc34e63195888ba696f2183ba5e2
+
+ since the driver would call RRFirstOutput without checking if randr has
+ been enabled, and it would crash in privates code.
+
+ reported by vereteran on #radeon
+
+ Signed-off-by: Dave Airlie <airlied@redhat.com>
+ Acked-on-irc-by: Michel Dänzer <michel.daenzer@amd.com>
+
+commit d669c34f140c000f88c4b4e464e44e6c8694f581
+Author: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Date: Mon Nov 21 11:35:40 2011 +1100
+
+ ddx/evergreen: Fix endian of ALU constants
+
+ The constants are written directly into a buffer object shared with the
+ card and we "forget" to swap them. This patch fixes it by doing the swap
+ in evergreen_set_alu_consts() in-place (ie, it modifies the buffer),
+ which should be fine with the way we use it in the ddx.
+
+ This makes everything work fine on my caicos card on a G5 including some
+ quik tests with Xv, gnome3 shell, etc...
+
+ Thanks a lot to Jerome Glisse for holding my hand through debugging that
+ (and finding the actual bug).
+
+ Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit 422bdd4fe6cb728e1dd08a56f6ee2d0f009cbfcb
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon Nov 14 09:39:16 2011 -0500
+
+ radeon: add missing FireMV pci id
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit 534fb6e413a909a9d1afd57d1c711844b7c5ddf4
+Author: Dave Airlie <airlied@redhat.com>
+Date: Fri Nov 11 10:26:51 2011 +0000
+
+ ati: enable bg none when fbcon succeeds and we are built against ABI after 10.
+
+ One less patch to keep carrying in Fedora.
+
+ Signed-off-by: Dave Airlie <airlied@redhat.com>
+
+commit 89452c08048c98fb5cc3dc551b3824be40d52cf2
+Author: Michel Dänzer <michel.daenzer@amd.com>
+Date: Tue Nov 8 11:23:11 2011 +0100
+
+ UMS: Guard references to PCITAG / pciTag with XSERVER_LIBPCIACCESS (bug #42690)
+
+ Should fix https://bugs.freedesktop.org/show_bug.cgi?id=42690 .
+
+ Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
+
+commit 5ec34ed95948f7164184551615c1fc4c3eef3b98
+Author: Ilija Hadzic <ihadzic@research.bell-labs.com>
+Date: Thu Nov 3 20:16:47 2011 -0400
+
+ DRI/DRI2: remove hard-coded limitation to 6 crtcs
+
+ DRM's hard limit to the number of CRTCs is 32. ATI DDX unnecessarily
+ clips this limit to 6 by hard coding initial assumption for
+ output->possible_crtcs mask to 0x7f (before it gets trimmed down to
+ what's really possible for a given output) and by allocating only 6
+ entries for for cursor_bo[] array in RADEONInfoRec.
+
+ Fix this and thus allow the ATI DDX to deal with as many CRTCs
+ as the DRM allows (32), so it is ready if anything with >6 CRTCs
+ comes out.
+
+ Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
+
+commit 4853ab2cdc3b97948c7cd69eaf4fff54f59774fc
+Author: Michel Dänzer <michel.daenzer@amd.com>
+Date: Fri Nov 4 12:15:53 2011 +0100
+
+ Turn compile time check into runtime check.
+
+ Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
+
+commit bcdb54fe16ebf2e239b84eebf20e8adfe5094bff
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Thu Oct 20 11:11:35 2011 -0400
+
+ check for xserver 1.9.4.901 to enable tiling by default
+
+ Previous xservers had a bug in the EXA code which caused
+ display corruption in some cases.
+
+ See:
+ https://bugs.freedesktop.org/show_bug.cgi?id=33929
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit edde94cba5321e6e51e7fd4d79dde5abc4944495
+Author: Michel Dänzer <michel.daenzer@amd.com>
+Date: Wed Nov 2 13:40:05 2011 +0100
+
+ Bump version post release.
+
commit 93459f842c2d8dc178a1954b8e05150fcb96ac9a
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Wed Nov 2 12:51:15 2011 +0100
diff --git a/debian/changelog b/debian/changelog
index a22f71b..913b223 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+xserver-xorg-video-ati (1:6.14.4-1) UNRELEASED; urgency=low
+
+ * New upstream release.
+
+ -- Cyril Brulebois <kibi@debian.org> Mon, 02 Apr 2012 20:10:07 +0000
+
xserver-xorg-video-ati (1:6.14.3-2) unstable; urgency=low
* Fix xinerama by cherry-picking:
commit 9425c50e93903fb64d9e569cfdc1e2c35d16ce25
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Thu Mar 29 00:19:12 2012 -0400
configure: bump version for release
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
diff --git a/configure.ac b/configure.ac
index 363e1d4..ae62cf2 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ([2.60])
AC_INIT([xf86-video-ati],
- [6.14.99],
+ [6.14.4],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
[xf86-video-ati])
commit dc18d771713ecd893c7d5833da6e0661093161dc
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Wed Mar 28 17:32:53 2012 -0400
configure: bump libdrm requirement for TN support
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
diff --git a/configure.ac b/configure.ac
index 0083325..363e1d4 100644
--- a/configure.ac
+++ b/configure.ac
@@ -141,7 +141,7 @@ if test "$DRI" = yes; then
AC_CHECK_HEADER(xf86drmMode.h,[DRM_MODE=yes],[DRM_MODE=no],[#include <stdint.h>
#include <stdlib.h>])
if test "x$DRM_MODE" = xyes; then
- PKG_CHECK_MODULES(LIBDRM_RADEON, [xorg-server >= 1.6.2 libdrm >= 2.4.31 libdrm_radeon],
+ PKG_CHECK_MODULES(LIBDRM_RADEON, [xorg-server >= 1.6.2 libdrm >= 2.4.33 libdrm_radeon],
[LIBDRM_RADEON=yes], [LIBDRM_RADEON=no])
if test "x$LIBDRM_RADEON" = xyes; then
commit 03535904a3e1542b3924d0a062c4b022ca196888
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Tue Mar 27 09:48:28 2012 -0400
radeon: man page updates
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
diff --git a/man/radeon.man b/man/radeon.man
index 55c5d02..e90979d 100644
--- a/man/radeon.man
+++ b/man/radeon.man
@@ -194,6 +194,8 @@ Radeon HD 6430/6450/6470/6490
.TP 12
.B CAYMAN
Radeon HD 6950/6970/6990
+.TP 12
+.B ARUBA
.PD
.SH CONFIGURATION DETAILS
Please refer to __xconfigfile__(__filemansuffix__) for general configuration
@@ -260,13 +262,25 @@ are supported for
.BI "Option \*qColorTiling\*q \*q" "boolean" \*q
The framebuffer can be addressed either in linear or tiled mode. Tiled mode can provide
significant performance benefits with 3D applications. Tiling will be disabled if the drm
-module is too old or if the current display configuration does not support it. KMS
-ColorTiling is not currently supported on R/RV/RS1XX, R/RV/RS2XX, and RS3XX.
+module is too old or if the current display configuration does not support it. On R600+
+this enables 1D tiling mode.
.br
The default value is
.B on
for R/RV3XX, R/RV4XX, R/RV5XX, RS6XX, RS740, R/RV6XX, R/RV7XX, RS780, RS880,
-EVERGREEN, and CAYMAN.
+EVERGREEN, and CAYMAN and
+.B off
+for R/RV/RS1XX, R/RV/RS2XX, and RS3XX.
+.TP
+.BI "Option \*qColorTiling2D\*q \*q" "boolean" \*q
+The framebuffer can be addressed either in linear, 1D, or 2D tiled modes. 2D tiled mode can
+provide significant performance benefits over 1D tiling with 3D applications. Tiling
+will be disabled if the drm module is too old or if the current display configuration
+does not support it. KMS ColorTiling2D is only supported on R600 and newer chips.
+.br
+The default value is
+.B off
+for R/RV6XX, R/RV7XX, RS780, RS880, EVERGREEN, and CAYMAN.
.TP
.BI "Option \*qEXAPixmaps\*q \*q" boolean \*q
Under KMS, to avoid thrashing pixmaps in/out of VRAM on low memory cards,
commit 6ed191c33caa33c12c2c6dafcba3a5ab1bf4a02f
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Tue Mar 20 19:57:53 2012 -0400
radeon/kms: add TN pci ids
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index 82da618..77e41ac 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -589,3 +589,10 @@
#define PCI_CHIP_CAICOS_6778 0x6778
#define PCI_CHIP_CAICOS_6779 0x6779
#define PCI_CHIP_CAICOS_677B 0x677B
+#define PCI_CHIP_ARUBA_9900 0x9900
+#define PCI_CHIP_ARUBA_9901 0x9901
+#define PCI_CHIP_ARUBA_9903 0x9903
+#define PCI_CHIP_ARUBA_9904 0x9904
+#define PCI_CHIP_ARUBA_990f 0x990f
+#define PCI_CHIP_ARUBA_9990 0x9990
+#define PCI_CHIP_ARUBA_9991 0x9991
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index ad3959b..3376438 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -590,3 +590,10 @@
"0x6778","CAICOS_6778","CAICOS",,,,,,"CAICOS"
"0x6779","CAICOS_6779","CAICOS",,,,,,"CAICOS"
"0x677B","CAICOS_677B","CAICOS",,,,,,"CAICOS"
+"0x9900","ARUBA_9900","ARUBA",1,,,,,"ARUBA"
+"0x9901","ARUBA_9901","ARUBA",,,,,,"ARUBA"
+"0x9903","ARUBA_9903","ARUBA",1,,,,,"ARUBA"
+"0x9904","ARUBA_9904","ARUBA",,,,,,"ARUBA"
+"0x990f","ARUBA_990f","ARUBA",,,,,,"ARUBA"
+"0x9990","ARUBA_9990","ARUBA",1,,,,,"ARUBA"
+"0x9991","ARUBA_9991","ARUBA",,,,,,"ARUBA"
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index 4ba84eb..a578825 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -509,4 +509,11 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x6778, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
{ 0x6779, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
{ 0x677B, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
+ { 0x9900, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
+ { 0x9901, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
+ { 0x9903, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
+ { 0x9904, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
+ { 0x990f, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
+ { 0x9990, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
+ { 0x9991, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
};
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index 8e567f9..e7f7379 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -509,5 +509,12 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_CAICOS_6778, "CAICOS" },
{ PCI_CHIP_CAICOS_6779, "CAICOS" },
{ PCI_CHIP_CAICOS_677B, "CAICOS" },
+ { PCI_CHIP_ARUBA_9900, "ARUBA" },
+ { PCI_CHIP_ARUBA_9901, "ARUBA" },
+ { PCI_CHIP_ARUBA_9903, "ARUBA" },
+ { PCI_CHIP_ARUBA_9904, "ARUBA" },
+ { PCI_CHIP_ARUBA_990f, "ARUBA" },
+ { PCI_CHIP_ARUBA_9990, "ARUBA" },
+ { PCI_CHIP_ARUBA_9991, "ARUBA" },
{ -1, NULL }
};
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index f271720..aef8d89 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -509,5 +509,12 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_CAICOS_6778, PCI_CHIP_CAICOS_6778, RES_SHARED_VGA },
{ PCI_CHIP_CAICOS_6779, PCI_CHIP_CAICOS_6779, RES_SHARED_VGA },
{ PCI_CHIP_CAICOS_677B, PCI_CHIP_CAICOS_677B, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9900, PCI_CHIP_ARUBA_9900, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9901, PCI_CHIP_ARUBA_9901, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9903, PCI_CHIP_ARUBA_9903, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9904, PCI_CHIP_ARUBA_9904, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_990f, PCI_CHIP_ARUBA_990f, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9990, PCI_CHIP_ARUBA_9990, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9991, PCI_CHIP_ARUBA_9991, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED }
};
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
index 8867052..681a6b8 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -509,5 +509,12 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6778, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6779, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_677B, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9900, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9901, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9903, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9904, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990f, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9990, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9991, 0 ),
{ 0, 0, 0 }
};
commit 55d65fcf33eb383e3fbc7a1d469ab68a70a7ab37
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Tue Mar 20 19:54:57 2012 -0400
radeon/kms: add support for TN (trinity) APUs
- KMS only
- Includes full EXA/Xv support
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
diff --git a/src/evergreen_accel.c b/src/evergreen_accel.c
index 3c76d38..581aaf6 100644
--- a/src/evergreen_accel.c
+++ b/src/evergreen_accel.c
@@ -661,7 +661,8 @@ evergreen_set_vtx_resource(ScrnInfoPtr pScrn, vtx_resource_t *res, uint32_t doma
(info->ChipFamily == CHIP_FAMILY_SUMO) ||
(info->ChipFamily == CHIP_FAMILY_SUMO2) ||
(info->ChipFamily == CHIP_FAMILY_CAICOS) ||
- (info->ChipFamily == CHIP_FAMILY_CAYMAN))
+ (info->ChipFamily == CHIP_FAMILY_CAYMAN) ||
+ (info->ChipFamily == CHIP_FAMILY_ARUBA))
evergreen_cp_set_surface_sync(pScrn, TC_ACTION_ENA_bit,
accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr,
res->bo,
@@ -864,8 +865,8 @@ evergreen_fix_scissor_coordinates(ScrnInfoPtr pScrn, int *x1, int *y1, int *x2,
if (*y2 == 0)
*y1 = 1;
- /* cayman only */
- if (info->ChipFamily == CHIP_FAMILY_CAYMAN) {
+ /* cayman/tn only */
+ if (info->ChipFamily >= CHIP_FAMILY_CAYMAN) {
/* cliprects aren't affected so we can use them to clip if we need
* a true 1x1 clip region
*/
@@ -970,7 +971,7 @@ evergreen_set_default_state(ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
- if (info->ChipFamily == CHIP_FAMILY_CAYMAN) {
+ if (info->ChipFamily >= CHIP_FAMILY_CAYMAN) {
cayman_set_default_state(pScrn);
return;
}
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index 1077a2d..cee3ec2 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -1958,7 +1958,7 @@ EVERGREENDrawInit(ScreenPtr pScreen)
if (!EVERGREENAllocShaders(pScrn, pScreen))
return FALSE;
- if (info->ChipFamily == CHIP_FAMILY_CAYMAN) {
+ if (info->ChipFamily >= CHIP_FAMILY_CAYMAN) {
if (!CAYMANLoadShaders(pScrn))
return FALSE;
} else {
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index c094bea..dda25e9 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -688,7 +688,7 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
Bool colorTilingDefault =
xorgGetVersion() >= XORG_VERSION_NUMERIC(1,9,4,901,0) &&
info->ChipFamily >= CHIP_FAMILY_R300 &&
- info->ChipFamily <= CHIP_FAMILY_CAYMAN;
+ info->ChipFamily <= CHIP_FAMILY_ARUBA;
/* 2D color tiling */
if (info->ChipFamily >= CHIP_FAMILY_R600) {
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 3123bcc..6690502 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -108,6 +108,7 @@ typedef enum {
CHIP_FAMILY_TURKS,
CHIP_FAMILY_CAICOS,
CHIP_FAMILY_CAYMAN,
+ CHIP_FAMILY_ARUBA,
CHIP_FAMILY_LAST
} RADEONChipFamily;
commit b5cf9bd693cf4090956add4c33c4fae9c3069a03
Author: Marek Olšák <maraeo@gmail.com>
Date: Wed Mar 7 11:01:40 2012 -0500
r6xx: initialize SX_MISC
If Mesa set it to 1, the DDX would not render anything = the monitor would
basically freeze.
agd5f: update emit count as well.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 8e6bffa..8d25424 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -1161,7 +1161,7 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
r600_fs_setup(pScrn, ib, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
// VGT
- BEGIN_BATCH(43);
+ BEGIN_BATCH(46);
PACK0(ib, VGT_MAX_VTX_INDX, 4);
E32(ib, 0xffffff); // VGT_MAX_VTX_INDX
E32(ib, 0); // VGT_MIN_VTX_INDX
@@ -1200,6 +1200,7 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
E32(ib, 0); // VGT_VTX_CNT_EN
EREG(ib, VGT_STRMOUT_BUFFER_EN, 0);
+ EREG(ib, SX_MISC, 0);
END_BATCH();
}
commit 355dc4295912c153f5333421594fa90aa119a056
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Tue Mar 6 15:52:40 2012 +0100
DRI2: Unreference buffers immediately when event wait info is invalidated.
Deferring this could result in trying to unreference buffers from a previous
server generation, i.e. accessing freed memory.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Christian König <Christian.koenig@amd.com>
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index cf905a1..8bd3f66 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -571,6 +571,22 @@ ListDelDRI2ClientEvents(ClientPtr client, struct xorg_list *entry)
}
Reply to: