xserver-xorg-video-ati: Changes to 'upstream-unstable'
Rebased ref, commits from common ancestor:
commit 5c256808cb5fea955eea96ffe9196473715156aa
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Wed Mar 17 23:47:50 2010 -0400
XAA: disable render accel
It's been reported broken for a while. Should fix
fdo bug 27151, others.
diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c
index dd1defd..36f25e7 100644
--- a/src/radeon_accelfuncs.c
+++ b/src/radeon_accelfuncs.c
@@ -1332,6 +1332,7 @@ FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a)
#endif
#ifdef RENDER
+ info->RenderAccel = FALSE;
if (info->RenderAccel && info->xaaReq.minorversion >= 2) {
a->CPUToScreenAlphaTextureFlags = XAA_RENDER_POWER_OF_2_TILE_ONLY;
commit a0683be5cc082bdbdd3bc4e9b52f39f423650946
Author: Dave Airlie <airlied@redhat.com>
Date: Thu Mar 18 12:36:25 2010 +1000
radeon: avoid using DRI1 init path on DRI2 driver.
I was playing with multi-seat and found this code, fixed
it up to be sane and more DRI2 like.
Signed-off-by: Dave Airlie <airlied@redhat.com>
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 1121044..399a6a7 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1151,31 +1151,11 @@ static const xf86CrtcConfigFuncsRec drmmode_xf86crtc_config_funcs = {
};
-Bool drmmode_pre_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, char *busId, char *driver_name, int cpp)
+Bool drmmode_pre_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int cpp)
{
xf86CrtcConfigPtr xf86_config;
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
int i;
- Bool ret;
-
- /* Create a bus Id */
- /* Low level DRM open */
- if (!pRADEONEnt->fd) {
- ret = DRIOpenDRMMaster(pScrn, SAREA_MAX, busId, driver_name);
- if (!ret) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "[dri] DRIGetVersion failed to open the DRM\n"
- "[dri] Disabling DRI.\n");
- return FALSE;
- }
- drmmode->fd = DRIMasterFD(pScrn);
- pRADEONEnt->fd = drmmode->fd;
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- " reusing fd for second head\n");
- drmmode->fd = pRADEONEnt->fd;
- }
xf86CrtcConfigInit(pScrn, &drmmode_xf86crtc_config_funcs);
xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
diff --git a/src/drmmode_display.h b/src/drmmode_display.h
index 1576d49..2e76259 100644
--- a/src/drmmode_display.h
+++ b/src/drmmode_display.h
@@ -74,7 +74,7 @@ typedef struct {
} drmmode_output_private_rec, *drmmode_output_private_ptr;
-extern Bool drmmode_pre_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, char *busId, char *driver_name, int cpp);
+extern Bool drmmode_pre_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int cpp);
extern Bool drmmode_set_bufmgr(ScrnInfoPtr pScrn, drmmode_ptr drmmode, struct radeon_bo_manager *bufmgr);
extern void drmmode_set_cursor(ScrnInfoPtr scrn, drmmode_ptr drmmode, int id, struct radeon_bo *bo);
void drmmode_adjust_frame(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int x, int y, int flags);
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 1f9c5d4..15e5e3f 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -362,12 +362,67 @@ static Bool radeon_alloc_dri(ScrnInfoPtr pScrn)
return TRUE;
}
+static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+ struct pci_device *dev = info->PciInfo;
+ char *busid;
+ drmSetVersion sv;
+ int err;
+
+ if (pRADEONEnt->fd) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ " reusing fd for second head\n");
+
+ info->dri2.drm_fd = pRADEONEnt->fd;
+ goto out;
+ }
+
+ busid = XNFprintf("pci:%04x:%02x:%02x.%d",
+ dev->domain, dev->bus, dev->dev, dev->func);
+
+ info->dri2.drm_fd = drmOpen("radeon", busid);
+ if (info->dri2.drm_fd == -1) {
+
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "[drm] Failed to open DRM device for %s: %s\n",
+ busid, strerror(errno));
+ xfree(busid);
+ return FALSE;
+ }
+ xfree(busid);
+
+ /* Check that what we opened was a master or a master-capable FD,
+ * by setting the version of the interface we'll use to talk to it.
+ * (see DRIOpenDRMMaster() in DRI1)
+ */
+ sv.drm_di_major = 1;
+ sv.drm_di_minor = 1;
+ sv.drm_dd_major = -1;
+ sv.drm_dd_minor = -1;
+ err = drmSetInterfaceVersion(info->dri2.drm_fd, &sv);
+ if (err != 0) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "[drm] failed to set drm interface version.\n");
+ drmClose(info->dri2.drm_fd);
+ info->dri2.drm_fd = -1;
+
+ return FALSE;
+ }
+
+ pRADEONEnt->fd = info->dri2.drm_fd;
+ out:
+ info->drmmode.fd = info->dri2.drm_fd;
+ info->dri->drmFD = info->dri2.drm_fd;
+ return TRUE;
+}
+
Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
{
RADEONInfoPtr info;
RADEONEntPtr pRADEONEnt;
DevUnion* pPriv;
- char *bus_id;
Gamma zeros = { 0.0, 0.0, 0.0 };
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
@@ -434,17 +489,16 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis");
- bus_id = DRICreatePCIBusID(info->PciInfo);
- if (drmmode_pre_init(pScrn, &info->drmmode, bus_id, "radeon", pScrn->bitsPerPixel / 8) == FALSE) {
- xfree(bus_id);
+ if (radeon_open_drm_master(pScrn) == FALSE) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n");
+ goto fail;
+ }
+ if (drmmode_pre_init(pScrn, &info->drmmode, pScrn->bitsPerPixel / 8) == FALSE) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n");
goto fail;
}
- info->dri->drmFD = info->drmmode.fd;
- info->dri2.drm_fd = info->drmmode.fd;
info->dri2.enabled = FALSE;
- xfree(bus_id);
info->dri->pKernelDRMVersion = drmGetVersion(info->dri->drmFD);
if (info->dri->pKernelDRMVersion == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
commit 080a5414593e9b59ed923f26aa6057747b0c868f
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Tue Mar 16 12:33:39 2010 -0400
kms: fix ums naming compat for DisplayPort
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 253ec1e..1121044 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -844,7 +844,7 @@ const char *output_names[] = { "None",
"LVDS",
"CTV",
"DIN",
- "DP",
+ "DisplayPort",
"HDMI",
"HDMI",
"TV",
@@ -889,6 +889,7 @@ drmmode_output_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int num)
case DRM_MODE_CONNECTOR_DVIA:
case DRM_MODE_CONNECTOR_HDMIA:
case DRM_MODE_CONNECTOR_HDMIB:
+ case DRM_MODE_CONNECTOR_DisplayPort:
snprintf(name, 32, "%s-%d", output_names[koutput->connector_type], koutput->connector_type_id - 1);
break;
default:
commit 819b4015349b5d8c5ffa5f979097599774fce5bb
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Mar 15 13:47:29 2010 -0400
dump version for rc release
diff --git a/configure.ac b/configure.ac
index d2c70f5..c1fae22 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-ati],
- 6.12.191,
+ 6.12.192,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-ati)
commit d3482a947e3731be4ed0b00b4e3079470700dc4c
Author: Michael Cree <mcree@orcon.net.nz>
Date: Fri Mar 12 22:23:31 2010 +1300
Fix some word accesses in AtomBios to work on all architectures.
The UINT16LE_TO_CPU(), etc., macros are used in the AtomBios code to
fix up endian issues but they do not address bad alignment or assist
architectures that cannot perform hardware byte or word accesses.
This patch inserts use of the ldw_u(), etc., interface of the Xserver
into certain AtomBios accesses to address alignment issues.
This resolves Debian bug 572311, namely that the driver when compiled
for generic Alpha architecture (i.e. doesn't use the byte-word extension)
resulted in no display output on certain Radeon cards.
Signed-off-by: Michael Cree <mcree@orcon.net.nz>
diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c
index c1279b8..ae27049 100644
--- a/src/AtomBios/CD_Operations.c
+++ b/src/AtomBios/CD_Operations.c
@@ -42,6 +42,7 @@ Revision History:
#include <X11/Xos.h>
#include "xorg-server.h"
+#include "compiler.h"
#include "Decoder.h"
@@ -230,7 +231,7 @@ UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].func(pParserTempData);
pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
}
- pParserTempData->IndirectIOTablePointer-=UINT16LE_TO_CPU(*(UINT16*)(pParserTempData->IndirectIOTablePointer+1));
+ pParserTempData->IndirectIOTablePointer-=UINT16LE_TO_CPU(ldw_u((uint16_t *)(pParserTempData->IndirectIOTablePointer+1)));
pParserTempData->IndirectIOTablePointer++;
return pParserTempData->IndirectData;
} else pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
@@ -267,8 +268,8 @@ VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)=
- CPU_TO_UINT32LE(pParserTempData->DestData32);
+ stl_u(CPU_TO_UINT32LE(pParserTempData->DestData32),
+ pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination);
}
VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
@@ -341,7 +342,7 @@ VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
+ pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
pParserTempData->Index+=pParserTempData->CurrentRegBlock;
switch(pParserTempData->Multipurpose.CurrentPort)
@@ -425,9 +426,9 @@ UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- UINT32 ret;
+ UINT32 ret;
- pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
+ pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
ret = UINT32LE_TO_CPU(*(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock));
return ret;
@@ -444,7 +445,7 @@ UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->CD_Mask.SrcAlignment=alignmentLowerWord;
- pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
+ pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
return pParserTempData->Index;
}
@@ -680,7 +681,7 @@ VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
- while ( UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP) != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE))
+ while ( UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP)) != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE))
{
if (*pParserTempData->pWorkingTableData->IP == 'c')
{
commit 488c9fd8300505cc6c0c2f8f0f00849f27cc5d63
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Mar 15 12:25:57 2010 -0400
r6xx/r7xx: fix domain handling in accel code
Noticed by Pauli and Michel on IRC.
Improves GetImage performace by a factor of ~10.
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 488291d..0d7e9f9 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -276,7 +276,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
- vs_setup (pScrn, accel_state->ib, &vs_conf);
+ vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
/* flush SQ cache */
cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
@@ -290,7 +290,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
- ps_setup (pScrn, accel_state->ib, &ps_conf);
+ ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
/* Render setup */
if (pm & 0x000000ff)
@@ -324,7 +324,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
- set_render_target(pScrn, accel_state->ib, &cb_conf);
+ set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM);
/* Interpolator setup */
/* one unused export from VS (VS_EXPORT_COUNT is zero based, count minus one) */
@@ -498,7 +498,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
- vs_setup (pScrn, accel_state->ib, &vs_conf);
+ vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
/* flush SQ cache */
cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
@@ -512,12 +512,12 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
- ps_setup (pScrn, accel_state->ib, &ps_conf);
+ ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
/* flush texture cache */
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
accel_state->src_size[0], accel_state->src_mc_addr[0],
- accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
/* Texture */
tex_res.id = 0;
@@ -554,7 +554,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
tex_samp.id = 0;
tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL;
@@ -598,7 +598,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
- set_render_target(pScrn, accel_state->ib, &cb_conf);
+ set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* Interpolator setup */
/* export tex coord from VS */
@@ -1281,7 +1281,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
/* flush texture cache */
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
accel_state->src_size[unit], accel_state->src_mc_addr[unit],
- accel_state->src_bo[unit], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[unit], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
/* Texture */
tex_res.id = unit;
@@ -1414,7 +1414,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
tex_samp.id = unit;
tex_samp.border_color = SQ_TEX_BORDER_COLOR_TRANS_BLACK;
@@ -1715,7 +1715,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
vs_conf.num_gprs = 3;
vs_conf.stack_size = 1;
vs_conf.bo = accel_state->shaders_bo;
- vs_setup (pScrn, accel_state->ib, &vs_conf);
+ vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
/* flush SQ cache */
cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
@@ -1729,7 +1729,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
- ps_setup (pScrn, accel_state->ib, &ps_conf);
+ ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
BEGIN_BATCH(9);
EREG(accel_state->ib, CB_TARGET_MASK, (0xf << TARGET0_ENABLE_shift));
@@ -1782,7 +1782,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
- set_render_target(pScrn, accel_state->ib, &cb_conf);
+ set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM);
/* Interpolator setup */
BEGIN_BATCH(21);
diff --git a/src/r600_state.h b/src/r600_state.h
index 0ee480b..1f2fbaa 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -281,26 +281,26 @@ wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib);
void
start_3d(ScrnInfoPtr pScrn, drmBufPtr ib);
void
-set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf);
+set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain);
void
cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_t size, uint64_t mc_addr,
struct radeon_bo *bo, uint32_t rdomains, uint32_t wdomain);
void
cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
void
-fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf);
+fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain);
void
-vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf);
+vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain);
void
-ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf);
+ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain);
void
set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf);
void
set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val);
void
-set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res);
+set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t domain);
void
-set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res);
+set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain);
void
set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s);
void
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index f9b3a90..7b55cec 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -257,7 +257,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
- vs_setup (pScrn, accel_state->ib, &vs_conf);
+ vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
/* flush SQ cache */
cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
@@ -271,7 +271,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
- ps_setup (pScrn, accel_state->ib, &ps_conf);
+ ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
/* PS alu constants */
set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps,
@@ -286,7 +286,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* flush texture cache */
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, accel_state->src_size[0],
accel_state->src_mc_addr[0],
- accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
/* Y texture */
tex_res.id = 0;
@@ -311,7 +311,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
tex_res.interlaced = 0;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* Y sampler */
tex_samp.id = 0;
@@ -331,7 +331,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
accel_state->src_size[0] / 4,
accel_state->src_mc_addr[0] + pPriv->planev_offset,
- accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
tex_res.id = 1;
tex_res.format = FMT_8;
@@ -346,7 +346,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_mc_addr[0] + pPriv->planev_offset;
tex_res.mip_base = accel_state->src_mc_addr[0] + pPriv->planev_offset;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* U or V sampler */
tex_samp.id = 1;
@@ -356,7 +356,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
accel_state->src_size[0] / 4,
accel_state->src_mc_addr[0] + pPriv->planeu_offset,
- accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
tex_res.id = 2;
tex_res.format = FMT_8;
@@ -371,7 +371,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_mc_addr[0] + pPriv->planeu_offset;
tex_res.mip_base = accel_state->src_mc_addr[0] + pPriv->planeu_offset;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* UV sampler */
tex_samp.id = 2;
@@ -385,7 +385,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* flush texture cache */
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, accel_state->src_size[0],
accel_state->src_mc_addr[0],
- accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
/* Y texture */
tex_res.id = 0;
@@ -413,7 +413,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
tex_res.interlaced = 0;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* Y sampler */
tex_samp.id = 0;
@@ -448,7 +448,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_mc_addr[0];
tex_res.mip_base = accel_state->src_mc_addr[0];
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* UV sampler */
tex_samp.id = 1;
@@ -488,7 +488,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
- set_render_target(pScrn, accel_state->ib, &cb_conf);
+ set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM);
/* Interpolator setup */
/* export tex coords from VS */
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 3ec9018..d7a95a4 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -222,7 +222,7 @@ sq_setup(ScrnInfoPtr pScrn, drmBufPtr ib, sq_config_t *sq_conf)
}
void
-set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf)
+set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain)
{
uint32_t cb_color_info;
int pitch, slice, h;
@@ -259,7 +259,7 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf)
BEGIN_BATCH(3 + 2);
EREG(ib, (CB_COLOR0_BASE + (4 * cb_conf->id)), (cb_conf->base >> 8));
- RELOC_BATCH(cb_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(cb_conf->bo, 0, domain);
END_BATCH();
// rv6xx workaround
@@ -276,11 +276,11 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf)
*/
BEGIN_BATCH(3 + 2);
EREG(ib, (CB_COLOR0_TILE + (4 * cb_conf->id)), (0 >> 8)); // CMASK per-tile data base/256
- RELOC_BATCH(cb_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(cb_conf->bo, 0, domain);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(ib, (CB_COLOR0_FRAG + (4 * cb_conf->id)), (0 >> 8)); // FMASK per-tile data base/256
- RELOC_BATCH(cb_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(cb_conf->bo, 0, domain);
END_BATCH();
BEGIN_BATCH(12);
// pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib
@@ -399,7 +399,7 @@ void cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
}
void
-fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf)
+fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_pgm_resources;
@@ -412,7 +412,7 @@ fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf)
BEGIN_BATCH(3 + 2);
EREG(ib, SQ_PGM_START_FS, fs_conf->shader_addr >> 8);
- RELOC_BATCH(fs_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(fs_conf->bo, domain, 0);
END_BATCH();
BEGIN_BATCH(6);
@@ -422,7 +422,7 @@ fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf)
}
void
-vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf)
+vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_pgm_resources;
@@ -439,7 +439,7 @@ vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf)
BEGIN_BATCH(3 + 2);
EREG(ib, SQ_PGM_START_VS, vs_conf->shader_addr >> 8);
- RELOC_BATCH(vs_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(vs_conf->bo, domain, 0);
END_BATCH();
BEGIN_BATCH(6);
@@ -449,7 +449,7 @@ vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf)
}
void
-ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf)
+ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_pgm_resources;
@@ -468,7 +468,7 @@ ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf)
BEGIN_BATCH(3 + 2);
EREG(ib, SQ_PGM_START_PS, ps_conf->shader_addr >> 8);
- RELOC_BATCH(ps_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(ps_conf->bo, domain, 0);
END_BATCH();
BEGIN_BATCH(9);
@@ -505,7 +505,7 @@ set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val)
}
void
-set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res)
+set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_vtx_constant_word2;
@@ -533,12 +533,12 @@ set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res)
E32(ib, 0); // 4: n/a
E32(ib, 0); // 5: n/a
E32(ib, SQ_TEX_VTX_VALID_BUFFER << SQ_VTX_CONSTANT_WORD6_0__TYPE_shift); // 6: TYPE
- RELOC_BATCH(res->bo, RADEON_GEM_DOMAIN_GTT, 0);
+ RELOC_BATCH(res->bo, domain, 0);
END_BATCH();
}
void
-set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res)
+set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
@@ -599,8 +599,8 @@ set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res)
E32(ib, sq_tex_resource_word4);
E32(ib, sq_tex_resource_word5);
E32(ib, sq_tex_resource_word6);
- RELOC_BATCH(tex_res->bo, RADEON_GEM_DOMAIN_VRAM, 0);
- RELOC_BATCH(tex_res->mip_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(tex_res->bo, domain, 0);
+ RELOC_BATCH(tex_res->mip_bo, domain, 0);
END_BATCH();
}
@@ -1085,7 +1085,7 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
// clear FS
fs_conf.bo = accel_state->shaders_bo;
- fs_setup(pScrn, ib, &fs_conf);
+ fs_setup(pScrn, ib, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
// VGT
BEGIN_BATCH(75);
@@ -1271,7 +1271,7 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
vtx_res.mem_req_size = 1;
vtx_res.vb_addr = accel_state->vb_mc_addr + accel_state->vb_start_op;
vtx_res.bo = accel_state->vb_bo;
- set_vtx_resource (pScrn, accel_state->ib, &vtx_res);
+ set_vtx_resource (pScrn, accel_state->ib, &vtx_res, RADEON_GEM_DOMAIN_GTT);
/* Draw */
draw_conf.prim_type = DI_PT_RECTLIST;
@@ -1288,7 +1288,7 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
/* sync dst surface */
cp_set_surface_sync(pScrn, accel_state->ib, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit),
accel_state->dst_size, accel_state->dst_mc_addr,
- accel_state->dst_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->dst_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
accel_state->vb_start_op = -1;
accel_state->ib_reset_op = 0;
commit 2ace2591d92fb6d3ce7a6453edb04b36a6c49a32
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Mar 15 12:03:58 2010 -0400
radeon: remove some leftover debugging output
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 4ed1c69..b627637 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -2866,8 +2866,6 @@ static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn)
else
mask = 3;
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "mask: %d\n", mask);
-
if (!RADEONAllocateControllers(pScrn, mask))
return FALSE;
commit 67e81c8f17ddde6eba633d2a5aef528e1d598d89
Author: Andrzej Hajda <andrzej.hajda@wp.pl>
Date: Wed Mar 10 18:19:35 2010 -0500
radeon: add support for pal on legacy IGP chips
Based on my initial non-working patch.
Fixes some element of fdo bug 12007
diff --git a/src/radeon_tv.c b/src/radeon_tv.c
index 6c083ce..74c82db 100644
--- a/src/radeon_tv.c
+++ b/src/radeon_tv.c
@@ -186,6 +186,21 @@ static const TVModeConstants availableTVModes[] =
8, /* crtcPLL_postDiv */
1022, /* pixToTV */
},
+ { /* PAL timing for 14 Mhz ref clk */
+ 800, /* horResolution */
+ 600, /* verResolution */
+ TV_STD_PAL, /* standard */
+ 1131, /* horTotal */
+ 742, /* verTotal */
+ 813, /* horStart */
+ 840, /* horSyncStart */
+ 633, /* verSyncStart */
+ 708369, /* defRestart */
+ 211, /* crtcPLL_N */
+ 9, /* crtcPLL_M */
+ 8, /* crtcPLL_postDiv */
+ 759, /* pixToTV */
+ },
};
#define N_AVAILABLE_MODES (sizeof(availableModes) / sizeof(availableModes[ 0 ]))
@@ -625,7 +640,7 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
hTotal = constPtr->horTotal;
@@ -754,7 +769,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->tv_crc_cntl = 0;
@@ -939,10 +954,9 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
n = PAL_TV_PLL_N_27;
p = PAL_TV_PLL_P_27;
} else {
- /* FIXME */
- m = PAL_TV_PLL_M_27;
- n = PAL_TV_PLL_N_27;
- p = PAL_TV_PLL_P_27;
+ m = PAL_TV_PLL_M_14;
+ n = PAL_TV_PLL_N_14;
+ p = PAL_TV_PLL_P_14;
}
}
save->tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) |
@@ -1080,7 +1094,7 @@ void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->crtc_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
@@ -1121,7 +1135,7 @@ void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->htotal_cntl = (constPtr->horTotal & 0x7 /*0xf*/) | RADEON_HTOT_CNTL_VGA_EN;
@@ -1184,7 +1198,7 @@ void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->crtc2_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
@@ -1225,7 +1239,7 @@ void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->htotal_cntl2 = (constPtr->horTotal & 0x7); /* 0xf */
diff --git a/src/radeon_tv.h b/src/radeon_tv.h
index 8d77a77..719452d 100644
--- a/src/radeon_tv.h
+++ b/src/radeon_tv.h
@@ -53,6 +53,10 @@
#define NTSC_TV_PLL_N_14 693
#define NTSC_TV_PLL_P_14 7
+#define PAL_TV_PLL_M_14 19
+#define PAL_TV_PLL_N_14 353
+#define PAL_TV_PLL_P_14 5
+
#define VERT_LEAD_IN_LINES 2
#define FRAC_BITS 0xe
#define FRAC_MASK 0x3fff
commit 3a44f1cb0d2bb748692b1024003de8ee88ca77a5
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Tue Mar 9 09:44:01 2010 -0500
atom: i2c gpio fixes
Basically a port of my kms patch. This allows us
to remove some quirks.
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 0fa53ff..bbe3d8e 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1515,9 +1515,10 @@ RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id)
{
RADEONInfoPtr info = RADEONPTR (pScrn);
atomDataTablesPtr atomDataPtr;
- ATOM_GPIO_I2C_ASSIGMENT gpio;
+ ATOM_GPIO_I2C_ASSIGMENT *gpio;
RADEONI2CBusRec i2c;
uint8_t crev, frev;
+ int i;
memset(&i2c, 0, sizeof(RADEONI2CBusRec));
i2c.valid = FALSE;
@@ -1531,48 +1532,53 @@ RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id)
return i2c;
}
- gpio = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[id];
- i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
- i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
- i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
- i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
- i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
- i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
- i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
- i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
- i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
- i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
- i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
- i2c.put_data_mask = (1 << gpio.ucDataEnShift);
- i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
- i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
- i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
- i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
- i2c.hw_line = gpio.sucI2cId.sbfAccess.bfI2C_LineMux;
- i2c.hw_capable = gpio.sucI2cId.sbfAccess.bfHW_Capable;
- i2c.valid = TRUE;
+ for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
+ gpio = &atomDataPtr->GPIO_I2C_Info->asGPIO_Info[i];
+ if (gpio->sucI2cId.ucAccess == id) {
+ i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
+ i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
+ i2c.put_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
+ i2c.put_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
+ i2c.get_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
+ i2c.get_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
+ i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
+ i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
+ i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
+ i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
+ i2c.put_clk_mask = (1 << gpio->ucClkEnShift);
+ i2c.put_data_mask = (1 << gpio->ucDataEnShift);
+ i2c.get_clk_mask = (1 << gpio->ucClkY_Shift);
+ i2c.get_data_mask = (1 << gpio->ucDataY_Shift);
+ i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
+ i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
+ i2c.hw_line = gpio->sucI2cId.ucAccess;
+ i2c.hw_capable = gpio->sucI2cId.sbfAccess.bfHW_Capable;
+ i2c.valid = TRUE;
+ break;
+ }
+ }
#if 0
ErrorF("id: %d\n", id);
- ErrorF("hw capable: %d\n", gpio.sucI2cId.sbfAccess.bfHW_Capable);
- ErrorF("hw engine id: %d\n", gpio.sucI2cId.sbfAccess.bfHW_EngineID);
- ErrorF("line mux %d\n", gpio.sucI2cId.sbfAccess.bfI2C_LineMux);
- ErrorF("mask_clk_reg: 0x%x\n", gpio.usClkMaskRegisterIndex * 4);
- ErrorF("mask_data_reg: 0x%x\n", gpio.usDataMaskRegisterIndex * 4);
- ErrorF("put_clk_reg: 0x%x\n", gpio.usClkEnRegisterIndex * 4);
- ErrorF("put_data_reg: 0x%x\n", gpio.usDataEnRegisterIndex * 4);
- ErrorF("get_clk_reg: 0x%x\n", gpio.usClkY_RegisterIndex * 4);
- ErrorF("get_data_reg: 0x%x\n", gpio.usDataY_RegisterIndex * 4);
- ErrorF("a_clk_reg: 0x%x\n", gpio.usClkA_RegisterIndex * 4);
- ErrorF("a_data_reg: 0x%x\n", gpio.usDataA_RegisterIndex * 4);
- ErrorF("mask_clk_mask: %d\n", gpio.ucClkMaskShift);
- ErrorF("mask_data_mask: %d\n", gpio.ucDataMaskShift);
- ErrorF("put_clk_mask: %d\n", gpio.ucClkEnShift);
- ErrorF("put_data_mask: %d\n", gpio.ucDataEnShift);
- ErrorF("get_clk_mask: %d\n", gpio.ucClkY_Shift);
- ErrorF("get_data_mask: %d\n", gpio.ucDataY_Shift);
- ErrorF("a_clk_mask: %d\n", gpio.ucClkA_Shift);
- ErrorF("a_data_mask: %d\n", gpio.ucDataA_Shift);
+ ErrorF("hw capable: %d\n", gpio->sucI2cId.sbfAccess.bfHW_Capable);
+ ErrorF("hw engine id: %d\n", gpio->sucI2cId.sbfAccess.bfHW_EngineID);
+ ErrorF("line mux %d\n", gpio->sucI2cId.sbfAccess.bfI2C_LineMux);
+ ErrorF("mask_clk_reg: 0x%x\n", gpio->usClkMaskRegisterIndex * 4);
+ ErrorF("mask_data_reg: 0x%x\n", gpio->usDataMaskRegisterIndex * 4);
+ ErrorF("put_clk_reg: 0x%x\n", gpio->usClkEnRegisterIndex * 4);
+ ErrorF("put_data_reg: 0x%x\n", gpio->usDataEnRegisterIndex * 4);
+ ErrorF("get_clk_reg: 0x%x\n", gpio->usClkY_RegisterIndex * 4);
+ ErrorF("get_data_reg: 0x%x\n", gpio->usDataY_RegisterIndex * 4);
+ ErrorF("a_clk_reg: 0x%x\n", gpio->usClkA_RegisterIndex * 4);
+ ErrorF("a_data_reg: 0x%x\n", gpio->usDataA_RegisterIndex * 4);
+ ErrorF("mask_clk_mask: %d\n", gpio->ucClkMaskShift);
+ ErrorF("mask_data_mask: %d\n", gpio->ucDataMaskShift);
+ ErrorF("put_clk_mask: %d\n", gpio->ucClkEnShift);
+ ErrorF("put_data_mask: %d\n", gpio->ucDataEnShift);
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