xserver-xorg-video-ati: Changes to 'upstream-unstable'
configure.ac | 2
src/AtomBios/CD_Operations.c | 17 +++--
src/ati_pciids_gen.h | 1
src/pcidb/ati_pciids.csv | 3 -
src/radeon_atombios.c | 109 ++++++++++++++++++--------------------
src/radeon_chipinfo_gen.h | 1
src/radeon_chipset_gen.h | 3 -
src/radeon_pci_chipset_gen.h | 1
src/radeon_pci_device_match_gen.h | 1
src/radeon_tv.c | 34 ++++++++---
src/radeon_tv.h | 4 +
11 files changed, 98 insertions(+), 78 deletions(-)
New commits:
commit 94202762f97d0cc8f2d0109e4f424f70a5460120
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Mar 15 13:37:08 2010 -0400
bump version for release
diff --git a/configure.ac b/configure.ac
index 6ff0ddb..c947e42 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-ati],
- 6.12.5,
+ 6.12.6,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-ati)
commit 54f69be224105d22fdae8df101efcefe0a1efee0
Author: Michael Cree <mcree@orcon.net.nz>
Date: Fri Mar 12 22:23:31 2010 +1300
Fix some word accesses in AtomBios to work on all architectures.
The UINT16LE_TO_CPU(), etc., macros are used in the AtomBios code to
fix up endian issues but they do not address bad alignment or assist
architectures that cannot perform hardware byte or word accesses.
This patch inserts use of the ldw_u(), etc., interface of the Xserver
into certain AtomBios accesses to address alignment issues.
This resolves Debian bug 572311, namely that the driver when compiled
for generic Alpha architecture (i.e. doesn't use the byte-word extension)
resulted in no display output on certain Radeon cards.
Signed-off-by: Michael Cree <mcree@orcon.net.nz>
diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c
index c1279b8..ae27049 100644
--- a/src/AtomBios/CD_Operations.c
+++ b/src/AtomBios/CD_Operations.c
@@ -42,6 +42,7 @@ Revision History:
#include <X11/Xos.h>
#include "xorg-server.h"
+#include "compiler.h"
#include "Decoder.h"
@@ -230,7 +231,7 @@ UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].func(pParserTempData);
pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
}
- pParserTempData->IndirectIOTablePointer-=UINT16LE_TO_CPU(*(UINT16*)(pParserTempData->IndirectIOTablePointer+1));
+ pParserTempData->IndirectIOTablePointer-=UINT16LE_TO_CPU(ldw_u((uint16_t *)(pParserTempData->IndirectIOTablePointer+1)));
pParserTempData->IndirectIOTablePointer++;
return pParserTempData->IndirectData;
} else pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
@@ -267,8 +268,8 @@ VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)=
- CPU_TO_UINT32LE(pParserTempData->DestData32);
+ stl_u(CPU_TO_UINT32LE(pParserTempData->DestData32),
+ pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination);
}
VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
@@ -341,7 +342,7 @@ VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
+ pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
pParserTempData->Index+=pParserTempData->CurrentRegBlock;
switch(pParserTempData->Multipurpose.CurrentPort)
@@ -425,9 +426,9 @@ UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- UINT32 ret;
+ UINT32 ret;
- pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
+ pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
ret = UINT32LE_TO_CPU(*(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock));
return ret;
@@ -444,7 +445,7 @@ UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->CD_Mask.SrcAlignment=alignmentLowerWord;
- pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
+ pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
return pParserTempData->Index;
}
@@ -680,7 +681,7 @@ VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
- while ( UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP) != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE))
+ while ( UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP)) != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE))
{
if (*pParserTempData->pWorkingTableData->IP == 'c')
{
commit d0bed11bb596200711b635d8b0b4ac7d9c5c7fd2
Author: Andrzej Hajda <andrzej.hajda@wp.pl>
Date: Wed Mar 10 18:19:35 2010 -0500
radeon: add support for pal on legacy IGP chips
Based on my initial non-working patch.
Fixes some element of fdo bug 12007
diff --git a/src/radeon_tv.c b/src/radeon_tv.c
index 6c083ce..74c82db 100644
--- a/src/radeon_tv.c
+++ b/src/radeon_tv.c
@@ -186,6 +186,21 @@ static const TVModeConstants availableTVModes[] =
8, /* crtcPLL_postDiv */
1022, /* pixToTV */
},
+ { /* PAL timing for 14 Mhz ref clk */
+ 800, /* horResolution */
+ 600, /* verResolution */
+ TV_STD_PAL, /* standard */
+ 1131, /* horTotal */
+ 742, /* verTotal */
+ 813, /* horStart */
+ 840, /* horSyncStart */
+ 633, /* verSyncStart */
+ 708369, /* defRestart */
+ 211, /* crtcPLL_N */
+ 9, /* crtcPLL_M */
+ 8, /* crtcPLL_postDiv */
+ 759, /* pixToTV */
+ },
};
#define N_AVAILABLE_MODES (sizeof(availableModes) / sizeof(availableModes[ 0 ]))
@@ -625,7 +640,7 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
hTotal = constPtr->horTotal;
@@ -754,7 +769,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->tv_crc_cntl = 0;
@@ -939,10 +954,9 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
n = PAL_TV_PLL_N_27;
p = PAL_TV_PLL_P_27;
} else {
- /* FIXME */
- m = PAL_TV_PLL_M_27;
- n = PAL_TV_PLL_N_27;
- p = PAL_TV_PLL_P_27;
+ m = PAL_TV_PLL_M_14;
+ n = PAL_TV_PLL_N_14;
+ p = PAL_TV_PLL_P_14;
}
}
save->tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) |
@@ -1080,7 +1094,7 @@ void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->crtc_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
@@ -1121,7 +1135,7 @@ void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->htotal_cntl = (constPtr->horTotal & 0x7 /*0xf*/) | RADEON_HTOT_CNTL_VGA_EN;
@@ -1184,7 +1198,7 @@ void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->crtc2_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
@@ -1225,7 +1239,7 @@ void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->htotal_cntl2 = (constPtr->horTotal & 0x7); /* 0xf */
diff --git a/src/radeon_tv.h b/src/radeon_tv.h
index 8d77a77..719452d 100644
--- a/src/radeon_tv.h
+++ b/src/radeon_tv.h
@@ -53,6 +53,10 @@
#define NTSC_TV_PLL_N_14 693
#define NTSC_TV_PLL_P_14 7
+#define PAL_TV_PLL_M_14 19
+#define PAL_TV_PLL_N_14 353
+#define PAL_TV_PLL_P_14 5
+
#define VERT_LEAD_IN_LINES 2
#define FRAC_BITS 0xe
#define FRAC_MASK 0x3fff
commit 999e088689ca3a60ad8e1f3953a6ddace4b12624
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Tue Mar 9 09:53:18 2010 -0500
atom: i2c gpio fixes
Basically a port of my kms patch. This allows us
to remove some quirks.
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 621a110..0ceef78 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1448,9 +1448,10 @@ RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id)
{
RADEONInfoPtr info = RADEONPTR (pScrn);
atomDataTablesPtr atomDataPtr;
- ATOM_GPIO_I2C_ASSIGMENT gpio;
+ ATOM_GPIO_I2C_ASSIGMENT *gpio;
RADEONI2CBusRec i2c;
uint8_t crev, frev;
+ int i;
memset(&i2c, 0, sizeof(RADEONI2CBusRec));
i2c.valid = FALSE;
@@ -1464,48 +1465,53 @@ RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id)
return i2c;
}
- gpio = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[id];
- i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
- i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
- i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
- i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
- i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
- i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
- i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
- i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
- i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
- i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
- i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
- i2c.put_data_mask = (1 << gpio.ucDataEnShift);
- i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
- i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
- i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
- i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
- i2c.hw_line = gpio.sucI2cId.sbfAccess.bfI2C_LineMux;
- i2c.hw_capable = gpio.sucI2cId.sbfAccess.bfHW_Capable;
- i2c.valid = TRUE;
+ for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
+ gpio = &atomDataPtr->GPIO_I2C_Info->asGPIO_Info[i];
+ if (gpio->sucI2cId.ucAccess == id) {
+ i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
+ i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
+ i2c.put_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
+ i2c.put_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
+ i2c.get_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
+ i2c.get_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
+ i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
+ i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
+ i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
+ i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
+ i2c.put_clk_mask = (1 << gpio->ucClkEnShift);
+ i2c.put_data_mask = (1 << gpio->ucDataEnShift);
+ i2c.get_clk_mask = (1 << gpio->ucClkY_Shift);
+ i2c.get_data_mask = (1 << gpio->ucDataY_Shift);
+ i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
+ i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
+ i2c.hw_line = gpio->sucI2cId.ucAccess;
+ i2c.hw_capable = gpio->sucI2cId.sbfAccess.bfHW_Capable;
+ i2c.valid = TRUE;
+ break;
+ }
+ }
#if 0
ErrorF("id: %d\n", id);
- ErrorF("hw capable: %d\n", gpio.sucI2cId.sbfAccess.bfHW_Capable);
- ErrorF("hw engine id: %d\n", gpio.sucI2cId.sbfAccess.bfHW_EngineID);
- ErrorF("line mux %d\n", gpio.sucI2cId.sbfAccess.bfI2C_LineMux);
- ErrorF("mask_clk_reg: 0x%x\n", gpio.usClkMaskRegisterIndex * 4);
- ErrorF("mask_data_reg: 0x%x\n", gpio.usDataMaskRegisterIndex * 4);
- ErrorF("put_clk_reg: 0x%x\n", gpio.usClkEnRegisterIndex * 4);
- ErrorF("put_data_reg: 0x%x\n", gpio.usDataEnRegisterIndex * 4);
- ErrorF("get_clk_reg: 0x%x\n", gpio.usClkY_RegisterIndex * 4);
- ErrorF("get_data_reg: 0x%x\n", gpio.usDataY_RegisterIndex * 4);
- ErrorF("a_clk_reg: 0x%x\n", gpio.usClkA_RegisterIndex * 4);
- ErrorF("a_data_reg: 0x%x\n", gpio.usDataA_RegisterIndex * 4);
- ErrorF("mask_clk_mask: %d\n", gpio.ucClkMaskShift);
- ErrorF("mask_data_mask: %d\n", gpio.ucDataMaskShift);
- ErrorF("put_clk_mask: %d\n", gpio.ucClkEnShift);
- ErrorF("put_data_mask: %d\n", gpio.ucDataEnShift);
- ErrorF("get_clk_mask: %d\n", gpio.ucClkY_Shift);
- ErrorF("get_data_mask: %d\n", gpio.ucDataY_Shift);
- ErrorF("a_clk_mask: %d\n", gpio.ucClkA_Shift);
- ErrorF("a_data_mask: %d\n", gpio.ucDataA_Shift);
+ ErrorF("hw capable: %d\n", gpio->sucI2cId.sbfAccess.bfHW_Capable);
+ ErrorF("hw engine id: %d\n", gpio->sucI2cId.sbfAccess.bfHW_EngineID);
+ ErrorF("line mux %d\n", gpio->sucI2cId.sbfAccess.bfI2C_LineMux);
+ ErrorF("mask_clk_reg: 0x%x\n", gpio->usClkMaskRegisterIndex * 4);
+ ErrorF("mask_data_reg: 0x%x\n", gpio->usDataMaskRegisterIndex * 4);
+ ErrorF("put_clk_reg: 0x%x\n", gpio->usClkEnRegisterIndex * 4);
+ ErrorF("put_data_reg: 0x%x\n", gpio->usDataEnRegisterIndex * 4);
+ ErrorF("get_clk_reg: 0x%x\n", gpio->usClkY_RegisterIndex * 4);
+ ErrorF("get_data_reg: 0x%x\n", gpio->usDataY_RegisterIndex * 4);
+ ErrorF("a_clk_reg: 0x%x\n", gpio->usClkA_RegisterIndex * 4);
+ ErrorF("a_data_reg: 0x%x\n", gpio->usDataA_RegisterIndex * 4);
+ ErrorF("mask_clk_mask: %d\n", gpio->ucClkMaskShift);
+ ErrorF("mask_data_mask: %d\n", gpio->ucDataMaskShift);
+ ErrorF("put_clk_mask: %d\n", gpio->ucClkEnShift);
+ ErrorF("put_data_mask: %d\n", gpio->ucDataEnShift);
+ ErrorF("get_clk_mask: %d\n", gpio->ucClkY_Shift);
+ ErrorF("get_data_mask: %d\n", gpio->ucDataY_Shift);
+ ErrorF("a_clk_mask: %d\n", gpio->ucClkA_Shift);
+ ErrorF("a_data_mask: %d\n", gpio->ucDataA_Shift);
#endif
return i2c;
@@ -1516,9 +1522,10 @@ rhdAtomParseI2CRecord(ScrnInfoPtr pScrn, atomBiosHandlePtr handle,
ATOM_I2C_RECORD *Record, int i)
{
RADEONInfoPtr info = RADEONPTR (pScrn);
+ uint8_t *temp = &Record->sucI2cId;
- info->BiosConnector[i].i2c_line_mux = Record->sucI2cId.bfI2C_LineMux;
- return RADEONLookupGPIOLineForDDC(pScrn, Record->sucI2cId.bfI2C_LineMux);
+ info->BiosConnector[i].i2c_line_mux = *temp;
+ return RADEONLookupGPIOLineForDDC(pScrn, *temp);
}
static void RADEONApplyATOMQuirks(ScrnInfoPtr pScrn, int index)
@@ -2249,7 +2256,7 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
info->BiosConnector[i].valid = TRUE;
info->BiosConnector[i].load_detection = TRUE;
info->BiosConnector[i].shared_ddc = FALSE;
- info->BiosConnector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux;
+ info->BiosConnector[i].output_id = ci.sucI2cId.ucAccess;
info->BiosConnector[i].devices = (1 << i);
info->BiosConnector[i].ConnectorType = ci.sucConnectorInfo.sbfAccess.bfConnectorType;
@@ -2263,21 +2270,9 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
(i == ATOM_DEVICE_TV2_INDEX) ||
(i == ATOM_DEVICE_CV_INDEX))
info->BiosConnector[i].ddc_i2c.valid = FALSE;
- else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
- (info->ChipFamily == CHIP_FAMILY_RS740)) {
- /* IGP DFP ports sometimes use non-standard gpio entries */
- if ((i == ATOM_DEVICE_DFP2_INDEX) && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
- info->BiosConnector[i].ddc_i2c =
- RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1);
- else if ((i == ATOM_DEVICE_DFP3_INDEX) && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
- info->BiosConnector[i].ddc_i2c =
- RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1);
- else
- info->BiosConnector[i].ddc_i2c =
- RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
- } else
+ else
info->BiosConnector[i].ddc_i2c =
- RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
+ RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.ucAccess);
if (!radeon_add_encoder(pScrn,
radeon_get_encoder_id_from_supported_device(pScrn, (1 << i),
commit 1df25c639dc494940f43b699dbe45ff7385d8a23
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Wed Mar 3 13:35:55 2010 -0500
radeon: add new RS880 pci id
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index 3f9691e..b9fcf51 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -453,3 +453,4 @@
#define PCI_CHIP_RS880_9712 0x9712
#define PCI_CHIP_RS880_9713 0x9713
#define PCI_CHIP_RS880_9714 0x9714
+#define PCI_CHIP_RS880_9715 0x9715
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 695d9a6..63d173b 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -453,4 +453,5 @@
"0x9711","RS880_9711","RS880",,1,,,1,"ATI Radeon 4100"
"0x9712","RS880_9712","RS880",1,1,,,1,"ATI Mobility Radeon HD 4200"
"0x9713","RS880_9713","RS880",1,1,,,1,"ATI Mobility Radeon 4100"
-"0x9714","RS880_9714","RS880",,1,,,1,"ATI RS880"
+"0x9714","RS880_9714","RS880",,1,,,1,"ATI Radeon HD 4290"
+"0x9715","RS880_9715","RS880",,1,,,1,"ATI Radeon HD 4290"
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index f93e4d1..52d6e5e 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -373,4 +373,5 @@ RADEONCardInfo RADEONCards[] = {
{ 0x9712, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 },
{ 0x9713, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 },
{ 0x9714, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 },
+ { 0x9715, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 },
};
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index fc41c3d..7629bda 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -372,6 +372,7 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RS880_9711, "ATI Radeon 4100" },
{ PCI_CHIP_RS880_9712, "ATI Mobility Radeon HD 4200" },
{ PCI_CHIP_RS880_9713, "ATI Mobility Radeon 4100" },
- { PCI_CHIP_RS880_9714, "ATI RS880" },
+ { PCI_CHIP_RS880_9714, "ATI Radeon HD 4290" },
+ { PCI_CHIP_RS880_9715, "ATI Radeon HD 4290" },
{ -1, NULL }
};
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index 1b85dcc..4a017cc 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -373,5 +373,6 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RS880_9712, PCI_CHIP_RS880_9712, RES_SHARED_VGA },
{ PCI_CHIP_RS880_9713, PCI_CHIP_RS880_9713, RES_SHARED_VGA },
{ PCI_CHIP_RS880_9714, PCI_CHIP_RS880_9714, RES_SHARED_VGA },
+ { PCI_CHIP_RS880_9715, PCI_CHIP_RS880_9715, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED }
};
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
index 64127bd..e50d71f 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -373,5 +373,6 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9712, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9713, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9714, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RS880_9715, 0 ),
{ 0, 0, 0 }
};
Reply to: