xserver-xorg-video-ati: Changes to 'debian-experimental'
ChangeLog | 86 ++++++++++++++++++++++++++++++
configure.ac | 3 -
debian/changelog | 14 ++++
debian/control | 1
src/AtomBios/CD_Operations.c | 17 +++--
src/ati_pciids_gen.h | 1
src/pcidb/ati_pciids.csv | 3 -
src/r600_exa.c | 26 ++++-----
src/r600_state.h | 12 ++--
src/r600_textured_videofuncs.c | 24 ++++----
src/r6xx_accel.c | 36 ++++++------
src/radeon_atombios.c | 108 +++++++++++++++++---------------------
src/radeon_chipinfo_gen.h | 1
src/radeon_chipset_gen.h | 3 -
src/radeon_crtc.c | 4 -
src/radeon_driver.c | 2
src/radeon_pci_chipset_gen.h | 1
src/radeon_pci_device_match_gen.h | 1
src/radeon_tv.c | 34 ++++++++---
src/radeon_tv.h | 4 +
20 files changed, 246 insertions(+), 135 deletions(-)
New commits:
commit 5bf0b9d0baf97b41cb29218a4db84cbef3e15f9e
Author: Brice Goglin <bgoglin@debian.org>
Date: Mon Mar 15 19:06:34 2010 +0100
Prepare changelog for upload
diff --git a/debian/changelog b/debian/changelog
index 3e4e302..c3401cb 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,10 +1,10 @@
-xserver-xorg-video-ati (1:6.12.192-1) UNRELEASED; urgency=low
+xserver-xorg-video-ati (1:6.12.192-1) experimental; urgency=low
* New upstream release candidate.
* Update package descriptions.
* Drop x11proto-xinerama-dev from Build-Depends, it is not used anymore.
- -- Brice Goglin <bgoglin@debian.org> Wed, 10 Mar 2010 22:55:05 +0100
+ -- Brice Goglin <bgoglin@debian.org> Mon, 15 Mar 2010 19:06:31 +0100
xserver-xorg-video-ati (1:6.12.191-1) experimental; urgency=low
commit 72911c6660a7af1a4f3a88b864f8dab6421dc71b
Author: Brice Goglin <bgoglin@debian.org>
Date: Mon Mar 15 19:06:29 2010 +0100
Drop x11proto-xinerama-dev from Build-Depends, it is not used anymore
diff --git a/debian/changelog b/debian/changelog
index 7699830..3e4e302 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -2,6 +2,7 @@ xserver-xorg-video-ati (1:6.12.192-1) UNRELEASED; urgency=low
* New upstream release candidate.
* Update package descriptions.
+ * Drop x11proto-xinerama-dev from Build-Depends, it is not used anymore.
-- Brice Goglin <bgoglin@debian.org> Wed, 10 Mar 2010 22:55:05 +0100
diff --git a/debian/control b/debian/control
index 7cae381..2210c53 100644
--- a/debian/control
+++ b/debian/control
@@ -11,7 +11,6 @@ Build-Depends:
x11proto-xext-dev,
x11proto-core-dev,
x11proto-video-dev,
- x11proto-xinerama-dev,
libgl1-mesa-dev | libgl-dev,
x11proto-fonts-dev,
x11proto-randr-dev (>= 1.2),
commit e335b58adb94dad30476ab31482cb38151a647b2
Author: Brice Goglin <bgoglin@debian.org>
Date: Mon Mar 15 19:04:51 2010 +0100
New upstream release candidate
diff --git a/ChangeLog b/ChangeLog
index 97d510d..8ba30c4 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,89 @@
+commit 819b4015349b5d8c5ffa5f979097599774fce5bb
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon Mar 15 13:47:29 2010 -0400
+
+ dump version for rc release
+
+commit d3482a947e3731be4ed0b00b4e3079470700dc4c
+Author: Michael Cree <mcree@orcon.net.nz>
+Date: Fri Mar 12 22:23:31 2010 +1300
+
+ Fix some word accesses in AtomBios to work on all architectures.
+
+ The UINT16LE_TO_CPU(), etc., macros are used in the AtomBios code to
+ fix up endian issues but they do not address bad alignment or assist
+ architectures that cannot perform hardware byte or word accesses.
+ This patch inserts use of the ldw_u(), etc., interface of the Xserver
+ into certain AtomBios accesses to address alignment issues.
+
+ This resolves Debian bug 572311, namely that the driver when compiled
+ for generic Alpha architecture (i.e. doesn't use the byte-word extension)
+ resulted in no display output on certain Radeon cards.
+
+ Signed-off-by: Michael Cree <mcree@orcon.net.nz>
+
+commit 488c9fd8300505cc6c0c2f8f0f00849f27cc5d63
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon Mar 15 12:25:57 2010 -0400
+
+ r6xx/r7xx: fix domain handling in accel code
+
+ Noticed by Pauli and Michel on IRC.
+
+ Improves GetImage performace by a factor of ~10.
+
+commit 2ace2591d92fb6d3ce7a6453edb04b36a6c49a32
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon Mar 15 12:03:58 2010 -0400
+
+ radeon: remove some leftover debugging output
+
+commit 67e81c8f17ddde6eba633d2a5aef528e1d598d89
+Author: Andrzej Hajda <andrzej.hajda@wp.pl>
+Date: Wed Mar 10 18:19:35 2010 -0500
+
+ radeon: add support for pal on legacy IGP chips
+
+ Based on my initial non-working patch.
+
+ Fixes some element of fdo bug 12007
+
+commit 3a44f1cb0d2bb748692b1024003de8ee88ca77a5
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Tue Mar 9 09:44:01 2010 -0500
+
+ atom: i2c gpio fixes
+
+ Basically a port of my kms patch. This allows us
+ to remove some quirks.
+
+commit d85cb40f516c67305e818302bec7ee817df4144c
+Author: Matt Turner <mattst88@gmail.com>
+Date: Sun Mar 7 14:24:35 2010 -0500
+
+ Don't check for Xinerama.
+
+ It doesn't seem to be used anywhere, so don't require it.
+
+ CC: Jerome Glisse <jglisse@redhat.com>
+ CC: Alex Deucher <alexdeucher@gmail.com>
+ CC: Dave Airlie <airlied@redhat.com>
+ Signed-off-by: Matt Turner <mattst88@gmail.com>
+
+commit e7b41f8cb082ed462d29bf3fc440072424cbd852
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Fri Mar 5 19:16:11 2010 -0500
+
+ radeon: disable frac fb div with new pll code
+
+ fixes fdo bug 26897
+
+commit 14aff767490c253cbcdd411f812e50b91673119e
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Wed Mar 3 13:31:19 2010 -0500
+
+ radeon: add new RS880 pci id
+
commit e6dc886634b38e4a36af7b5f0b23299d5acd7244
Author: Dave Airlie <airlied@redhat.com>
Date: Tue Mar 2 10:25:15 2010 +1000
diff --git a/debian/changelog b/debian/changelog
index 0ae0221..7699830 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,5 +1,6 @@
-xserver-xorg-video-ati (1:6.12.191-2) UNRELEASED; urgency=low
+xserver-xorg-video-ati (1:6.12.192-1) UNRELEASED; urgency=low
+ * New upstream release candidate.
* Update package descriptions.
-- Brice Goglin <bgoglin@debian.org> Wed, 10 Mar 2010 22:55:05 +0100
commit 4f7721310da7fd9926062097175c5ec77024f003
Author: Brice Goglin <bgoglin@debian.org>
Date: Mon Mar 15 18:53:40 2010 +0100
Prepare changelog for upload
diff --git a/debian/changelog b/debian/changelog
index 7122ca1..3233e17 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,10 +1,10 @@
-xserver-xorg-video-ati (1:6.12.6-1) UNRELEASED; urgency=low
+xserver-xorg-video-ati (1:6.12.6-1) unstable; urgency=low
* New upstream release.
+ Fix some word accesses in AtomBios to work on all architectures,
closes: #572311.
- -- Brice Goglin <bgoglin@debian.org> Mon, 15 Mar 2010 18:50:41 +0100
+ -- Brice Goglin <bgoglin@debian.org> Mon, 15 Mar 2010 18:53:23 +0100
xserver-xorg-video-ati (1:6.12.5-1) unstable; urgency=low
commit 582e7d66ce9b404a798f76fdeba88e246f16a0d7
Author: Brice Goglin <bgoglin@debian.org>
Date: Mon Mar 15 18:53:18 2010 +0100
New upstream release
diff --git a/ChangeLog b/ChangeLog
index f4e75fc..2857018 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,52 @@
+commit 94202762f97d0cc8f2d0109e4f424f70a5460120
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon Mar 15 13:37:08 2010 -0400
+
+ bump version for release
+
+commit 54f69be224105d22fdae8df101efcefe0a1efee0
+Author: Michael Cree <mcree@orcon.net.nz>
+Date: Fri Mar 12 22:23:31 2010 +1300
+
+ Fix some word accesses in AtomBios to work on all architectures.
+
+ The UINT16LE_TO_CPU(), etc., macros are used in the AtomBios code to
+ fix up endian issues but they do not address bad alignment or assist
+ architectures that cannot perform hardware byte or word accesses.
+ This patch inserts use of the ldw_u(), etc., interface of the Xserver
+ into certain AtomBios accesses to address alignment issues.
+
+ This resolves Debian bug 572311, namely that the driver when compiled
+ for generic Alpha architecture (i.e. doesn't use the byte-word extension)
+ resulted in no display output on certain Radeon cards.
+
+ Signed-off-by: Michael Cree <mcree@orcon.net.nz>
+
+commit d0bed11bb596200711b635d8b0b4ac7d9c5c7fd2
+Author: Andrzej Hajda <andrzej.hajda@wp.pl>
+Date: Wed Mar 10 18:19:35 2010 -0500
+
+ radeon: add support for pal on legacy IGP chips
+
+ Based on my initial non-working patch.
+
+ Fixes some element of fdo bug 12007
+
+commit 999e088689ca3a60ad8e1f3953a6ddace4b12624
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Tue Mar 9 09:53:18 2010 -0500
+
+ atom: i2c gpio fixes
+
+ Basically a port of my kms patch. This allows us
+ to remove some quirks.
+
+commit 1df25c639dc494940f43b699dbe45ff7385d8a23
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Wed Mar 3 13:35:55 2010 -0500
+
+ radeon: add new RS880 pci id
+
commit 802073aea2cadc446778902b344221ad2484dc34
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Tue Mar 2 20:46:06 2010 -0500
diff --git a/debian/changelog b/debian/changelog
index 863ae8b..7122ca1 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,11 @@
+xserver-xorg-video-ati (1:6.12.6-1) UNRELEASED; urgency=low
+
+ * New upstream release.
+ + Fix some word accesses in AtomBios to work on all architectures,
+ closes: #572311.
+
+ -- Brice Goglin <bgoglin@debian.org> Mon, 15 Mar 2010 18:50:41 +0100
+
xserver-xorg-video-ati (1:6.12.5-1) unstable; urgency=low
* New upstream release, closes: #572306.
commit 819b4015349b5d8c5ffa5f979097599774fce5bb
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Mar 15 13:47:29 2010 -0400
dump version for rc release
diff --git a/configure.ac b/configure.ac
index d2c70f5..c1fae22 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-ati],
- 6.12.191,
+ 6.12.192,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-ati)
commit 94202762f97d0cc8f2d0109e4f424f70a5460120
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Mar 15 13:37:08 2010 -0400
bump version for release
diff --git a/configure.ac b/configure.ac
index 6ff0ddb..c947e42 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-ati],
- 6.12.5,
+ 6.12.6,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-ati)
commit 54f69be224105d22fdae8df101efcefe0a1efee0
Author: Michael Cree <mcree@orcon.net.nz>
Date: Fri Mar 12 22:23:31 2010 +1300
Fix some word accesses in AtomBios to work on all architectures.
The UINT16LE_TO_CPU(), etc., macros are used in the AtomBios code to
fix up endian issues but they do not address bad alignment or assist
architectures that cannot perform hardware byte or word accesses.
This patch inserts use of the ldw_u(), etc., interface of the Xserver
into certain AtomBios accesses to address alignment issues.
This resolves Debian bug 572311, namely that the driver when compiled
for generic Alpha architecture (i.e. doesn't use the byte-word extension)
resulted in no display output on certain Radeon cards.
Signed-off-by: Michael Cree <mcree@orcon.net.nz>
diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c
index c1279b8..ae27049 100644
--- a/src/AtomBios/CD_Operations.c
+++ b/src/AtomBios/CD_Operations.c
@@ -42,6 +42,7 @@ Revision History:
#include <X11/Xos.h>
#include "xorg-server.h"
+#include "compiler.h"
#include "Decoder.h"
@@ -230,7 +231,7 @@ UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].func(pParserTempData);
pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
}
- pParserTempData->IndirectIOTablePointer-=UINT16LE_TO_CPU(*(UINT16*)(pParserTempData->IndirectIOTablePointer+1));
+ pParserTempData->IndirectIOTablePointer-=UINT16LE_TO_CPU(ldw_u((uint16_t *)(pParserTempData->IndirectIOTablePointer+1)));
pParserTempData->IndirectIOTablePointer++;
return pParserTempData->IndirectData;
} else pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
@@ -267,8 +268,8 @@ VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)=
- CPU_TO_UINT32LE(pParserTempData->DestData32);
+ stl_u(CPU_TO_UINT32LE(pParserTempData->DestData32),
+ pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination);
}
VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
@@ -341,7 +342,7 @@ VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
+ pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
pParserTempData->Index+=pParserTempData->CurrentRegBlock;
switch(pParserTempData->Multipurpose.CurrentPort)
@@ -425,9 +426,9 @@ UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- UINT32 ret;
+ UINT32 ret;
- pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
+ pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
ret = UINT32LE_TO_CPU(*(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock));
return ret;
@@ -444,7 +445,7 @@ UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->CD_Mask.SrcAlignment=alignmentLowerWord;
- pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
+ pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
return pParserTempData->Index;
}
@@ -680,7 +681,7 @@ VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
- while ( UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP) != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE))
+ while ( UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP)) != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE))
{
if (*pParserTempData->pWorkingTableData->IP == 'c')
{
commit d3482a947e3731be4ed0b00b4e3079470700dc4c
Author: Michael Cree <mcree@orcon.net.nz>
Date: Fri Mar 12 22:23:31 2010 +1300
Fix some word accesses in AtomBios to work on all architectures.
The UINT16LE_TO_CPU(), etc., macros are used in the AtomBios code to
fix up endian issues but they do not address bad alignment or assist
architectures that cannot perform hardware byte or word accesses.
This patch inserts use of the ldw_u(), etc., interface of the Xserver
into certain AtomBios accesses to address alignment issues.
This resolves Debian bug 572311, namely that the driver when compiled
for generic Alpha architecture (i.e. doesn't use the byte-word extension)
resulted in no display output on certain Radeon cards.
Signed-off-by: Michael Cree <mcree@orcon.net.nz>
diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c
index c1279b8..ae27049 100644
--- a/src/AtomBios/CD_Operations.c
+++ b/src/AtomBios/CD_Operations.c
@@ -42,6 +42,7 @@ Revision History:
#include <X11/Xos.h>
#include "xorg-server.h"
+#include "compiler.h"
#include "Decoder.h"
@@ -230,7 +231,7 @@ UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].func(pParserTempData);
pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
}
- pParserTempData->IndirectIOTablePointer-=UINT16LE_TO_CPU(*(UINT16*)(pParserTempData->IndirectIOTablePointer+1));
+ pParserTempData->IndirectIOTablePointer-=UINT16LE_TO_CPU(ldw_u((uint16_t *)(pParserTempData->IndirectIOTablePointer+1)));
pParserTempData->IndirectIOTablePointer++;
return pParserTempData->IndirectData;
} else pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
@@ -267,8 +268,8 @@ VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)=
- CPU_TO_UINT32LE(pParserTempData->DestData32);
+ stl_u(CPU_TO_UINT32LE(pParserTempData->DestData32),
+ pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination);
}
VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
@@ -341,7 +342,7 @@ VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
+ pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
pParserTempData->Index+=pParserTempData->CurrentRegBlock;
switch(pParserTempData->Multipurpose.CurrentPort)
@@ -425,9 +426,9 @@ UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- UINT32 ret;
+ UINT32 ret;
- pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
+ pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
ret = UINT32LE_TO_CPU(*(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock));
return ret;
@@ -444,7 +445,7 @@ UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->CD_Mask.SrcAlignment=alignmentLowerWord;
- pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
+ pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
return pParserTempData->Index;
}
@@ -680,7 +681,7 @@ VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
- while ( UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP) != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE))
+ while ( UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP)) != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE))
{
if (*pParserTempData->pWorkingTableData->IP == 'c')
{
commit 488c9fd8300505cc6c0c2f8f0f00849f27cc5d63
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Mar 15 12:25:57 2010 -0400
r6xx/r7xx: fix domain handling in accel code
Noticed by Pauli and Michel on IRC.
Improves GetImage performace by a factor of ~10.
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 488291d..0d7e9f9 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -276,7 +276,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
- vs_setup (pScrn, accel_state->ib, &vs_conf);
+ vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
/* flush SQ cache */
cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
@@ -290,7 +290,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
- ps_setup (pScrn, accel_state->ib, &ps_conf);
+ ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
/* Render setup */
if (pm & 0x000000ff)
@@ -324,7 +324,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
- set_render_target(pScrn, accel_state->ib, &cb_conf);
+ set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM);
/* Interpolator setup */
/* one unused export from VS (VS_EXPORT_COUNT is zero based, count minus one) */
@@ -498,7 +498,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
- vs_setup (pScrn, accel_state->ib, &vs_conf);
+ vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
/* flush SQ cache */
cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
@@ -512,12 +512,12 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
- ps_setup (pScrn, accel_state->ib, &ps_conf);
+ ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
/* flush texture cache */
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
accel_state->src_size[0], accel_state->src_mc_addr[0],
- accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
/* Texture */
tex_res.id = 0;
@@ -554,7 +554,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
tex_samp.id = 0;
tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL;
@@ -598,7 +598,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
- set_render_target(pScrn, accel_state->ib, &cb_conf);
+ set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* Interpolator setup */
/* export tex coord from VS */
@@ -1281,7 +1281,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
/* flush texture cache */
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
accel_state->src_size[unit], accel_state->src_mc_addr[unit],
- accel_state->src_bo[unit], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[unit], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
/* Texture */
tex_res.id = unit;
@@ -1414,7 +1414,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
tex_samp.id = unit;
tex_samp.border_color = SQ_TEX_BORDER_COLOR_TRANS_BLACK;
@@ -1715,7 +1715,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
vs_conf.num_gprs = 3;
vs_conf.stack_size = 1;
vs_conf.bo = accel_state->shaders_bo;
- vs_setup (pScrn, accel_state->ib, &vs_conf);
+ vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
/* flush SQ cache */
cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
@@ -1729,7 +1729,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
- ps_setup (pScrn, accel_state->ib, &ps_conf);
+ ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
BEGIN_BATCH(9);
EREG(accel_state->ib, CB_TARGET_MASK, (0xf << TARGET0_ENABLE_shift));
@@ -1782,7 +1782,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
- set_render_target(pScrn, accel_state->ib, &cb_conf);
+ set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM);
/* Interpolator setup */
BEGIN_BATCH(21);
diff --git a/src/r600_state.h b/src/r600_state.h
index 0ee480b..1f2fbaa 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -281,26 +281,26 @@ wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib);
void
start_3d(ScrnInfoPtr pScrn, drmBufPtr ib);
void
-set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf);
+set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain);
void
cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_t size, uint64_t mc_addr,
struct radeon_bo *bo, uint32_t rdomains, uint32_t wdomain);
void
cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
void
-fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf);
+fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain);
void
-vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf);
+vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain);
void
-ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf);
+ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain);
void
set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf);
void
set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val);
void
-set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res);
+set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t domain);
void
-set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res);
+set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain);
void
set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s);
void
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index f9b3a90..7b55cec 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -257,7 +257,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
- vs_setup (pScrn, accel_state->ib, &vs_conf);
+ vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
/* flush SQ cache */
cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
@@ -271,7 +271,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
- ps_setup (pScrn, accel_state->ib, &ps_conf);
+ ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
/* PS alu constants */
set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps,
@@ -286,7 +286,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* flush texture cache */
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, accel_state->src_size[0],
accel_state->src_mc_addr[0],
- accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
/* Y texture */
tex_res.id = 0;
@@ -311,7 +311,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
tex_res.interlaced = 0;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* Y sampler */
tex_samp.id = 0;
@@ -331,7 +331,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
accel_state->src_size[0] / 4,
accel_state->src_mc_addr[0] + pPriv->planev_offset,
- accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
tex_res.id = 1;
tex_res.format = FMT_8;
@@ -346,7 +346,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_mc_addr[0] + pPriv->planev_offset;
tex_res.mip_base = accel_state->src_mc_addr[0] + pPriv->planev_offset;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* U or V sampler */
tex_samp.id = 1;
@@ -356,7 +356,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
accel_state->src_size[0] / 4,
accel_state->src_mc_addr[0] + pPriv->planeu_offset,
- accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
tex_res.id = 2;
tex_res.format = FMT_8;
@@ -371,7 +371,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_mc_addr[0] + pPriv->planeu_offset;
tex_res.mip_base = accel_state->src_mc_addr[0] + pPriv->planeu_offset;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* UV sampler */
tex_samp.id = 2;
@@ -385,7 +385,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* flush texture cache */
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, accel_state->src_size[0],
accel_state->src_mc_addr[0],
- accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
/* Y texture */
tex_res.id = 0;
@@ -413,7 +413,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
tex_res.interlaced = 0;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* Y sampler */
tex_samp.id = 0;
@@ -448,7 +448,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_mc_addr[0];
tex_res.mip_base = accel_state->src_mc_addr[0];
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* UV sampler */
tex_samp.id = 1;
@@ -488,7 +488,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
- set_render_target(pScrn, accel_state->ib, &cb_conf);
+ set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM);
/* Interpolator setup */
/* export tex coords from VS */
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 3ec9018..d7a95a4 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -222,7 +222,7 @@ sq_setup(ScrnInfoPtr pScrn, drmBufPtr ib, sq_config_t *sq_conf)
}
void
-set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf)
+set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain)
{
uint32_t cb_color_info;
int pitch, slice, h;
@@ -259,7 +259,7 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf)
BEGIN_BATCH(3 + 2);
EREG(ib, (CB_COLOR0_BASE + (4 * cb_conf->id)), (cb_conf->base >> 8));
- RELOC_BATCH(cb_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(cb_conf->bo, 0, domain);
END_BATCH();
// rv6xx workaround
@@ -276,11 +276,11 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf)
*/
BEGIN_BATCH(3 + 2);
EREG(ib, (CB_COLOR0_TILE + (4 * cb_conf->id)), (0 >> 8)); // CMASK per-tile data base/256
- RELOC_BATCH(cb_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(cb_conf->bo, 0, domain);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(ib, (CB_COLOR0_FRAG + (4 * cb_conf->id)), (0 >> 8)); // FMASK per-tile data base/256
- RELOC_BATCH(cb_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(cb_conf->bo, 0, domain);
END_BATCH();
BEGIN_BATCH(12);
// pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib
@@ -399,7 +399,7 @@ void cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
}
void
-fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf)
+fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_pgm_resources;
@@ -412,7 +412,7 @@ fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf)
BEGIN_BATCH(3 + 2);
EREG(ib, SQ_PGM_START_FS, fs_conf->shader_addr >> 8);
- RELOC_BATCH(fs_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(fs_conf->bo, domain, 0);
END_BATCH();
BEGIN_BATCH(6);
@@ -422,7 +422,7 @@ fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf)
}
void
-vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf)
+vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_pgm_resources;
@@ -439,7 +439,7 @@ vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf)
BEGIN_BATCH(3 + 2);
EREG(ib, SQ_PGM_START_VS, vs_conf->shader_addr >> 8);
- RELOC_BATCH(vs_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(vs_conf->bo, domain, 0);
END_BATCH();
BEGIN_BATCH(6);
@@ -449,7 +449,7 @@ vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf)
}
void
-ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf)
+ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_pgm_resources;
@@ -468,7 +468,7 @@ ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf)
BEGIN_BATCH(3 + 2);
EREG(ib, SQ_PGM_START_PS, ps_conf->shader_addr >> 8);
- RELOC_BATCH(ps_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(ps_conf->bo, domain, 0);
END_BATCH();
BEGIN_BATCH(9);
@@ -505,7 +505,7 @@ set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val)
}
void
-set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res)
+set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_vtx_constant_word2;
@@ -533,12 +533,12 @@ set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res)
E32(ib, 0); // 4: n/a
E32(ib, 0); // 5: n/a
E32(ib, SQ_TEX_VTX_VALID_BUFFER << SQ_VTX_CONSTANT_WORD6_0__TYPE_shift); // 6: TYPE
- RELOC_BATCH(res->bo, RADEON_GEM_DOMAIN_GTT, 0);
+ RELOC_BATCH(res->bo, domain, 0);
END_BATCH();
}
void
-set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res)
+set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
@@ -599,8 +599,8 @@ set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res)
E32(ib, sq_tex_resource_word4);
E32(ib, sq_tex_resource_word5);
E32(ib, sq_tex_resource_word6);
- RELOC_BATCH(tex_res->bo, RADEON_GEM_DOMAIN_VRAM, 0);
- RELOC_BATCH(tex_res->mip_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(tex_res->bo, domain, 0);
+ RELOC_BATCH(tex_res->mip_bo, domain, 0);
END_BATCH();
}
@@ -1085,7 +1085,7 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
// clear FS
fs_conf.bo = accel_state->shaders_bo;
- fs_setup(pScrn, ib, &fs_conf);
+ fs_setup(pScrn, ib, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
// VGT
BEGIN_BATCH(75);
@@ -1271,7 +1271,7 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
vtx_res.mem_req_size = 1;
vtx_res.vb_addr = accel_state->vb_mc_addr + accel_state->vb_start_op;
vtx_res.bo = accel_state->vb_bo;
- set_vtx_resource (pScrn, accel_state->ib, &vtx_res);
+ set_vtx_resource (pScrn, accel_state->ib, &vtx_res, RADEON_GEM_DOMAIN_GTT);
/* Draw */
draw_conf.prim_type = DI_PT_RECTLIST;
@@ -1288,7 +1288,7 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
/* sync dst surface */
cp_set_surface_sync(pScrn, accel_state->ib, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit),
accel_state->dst_size, accel_state->dst_mc_addr,
- accel_state->dst_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->dst_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
accel_state->vb_start_op = -1;
accel_state->ib_reset_op = 0;
commit 2ace2591d92fb6d3ce7a6453edb04b36a6c49a32
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Mar 15 12:03:58 2010 -0400
radeon: remove some leftover debugging output
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 4ed1c69..b627637 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -2866,8 +2866,6 @@ static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn)
else
mask = 3;
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "mask: %d\n", mask);
-
if (!RADEONAllocateControllers(pScrn, mask))
return FALSE;
commit d0bed11bb596200711b635d8b0b4ac7d9c5c7fd2
Author: Andrzej Hajda <andrzej.hajda@wp.pl>
Date: Wed Mar 10 18:19:35 2010 -0500
radeon: add support for pal on legacy IGP chips
Based on my initial non-working patch.
Fixes some element of fdo bug 12007
diff --git a/src/radeon_tv.c b/src/radeon_tv.c
index 6c083ce..74c82db 100644
--- a/src/radeon_tv.c
+++ b/src/radeon_tv.c
@@ -186,6 +186,21 @@ static const TVModeConstants availableTVModes[] =
8, /* crtcPLL_postDiv */
1022, /* pixToTV */
},
+ { /* PAL timing for 14 Mhz ref clk */
+ 800, /* horResolution */
+ 600, /* verResolution */
+ TV_STD_PAL, /* standard */
+ 1131, /* horTotal */
+ 742, /* verTotal */
+ 813, /* horStart */
+ 840, /* horSyncStart */
+ 633, /* verSyncStart */
+ 708369, /* defRestart */
+ 211, /* crtcPLL_N */
+ 9, /* crtcPLL_M */
+ 8, /* crtcPLL_postDiv */
+ 759, /* pixToTV */
+ },
};
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