xserver-xorg-video-ati: Changes to 'upstream-experimental'
configure.ac | 3 -
src/AtomBios/CD_Operations.c | 17 +++--
src/ati_pciids_gen.h | 1
src/pcidb/ati_pciids.csv | 3 -
src/r600_exa.c | 26 ++++-----
src/r600_state.h | 12 ++--
src/r600_textured_videofuncs.c | 24 ++++----
src/r6xx_accel.c | 36 ++++++------
src/radeon_atombios.c | 108 +++++++++++++++++---------------------
src/radeon_chipinfo_gen.h | 1
src/radeon_chipset_gen.h | 3 -
src/radeon_crtc.c | 4 -
src/radeon_driver.c | 2
src/radeon_pci_chipset_gen.h | 1
src/radeon_pci_device_match_gen.h | 1
src/radeon_tv.c | 34 ++++++++---
src/radeon_tv.h | 4 +
17 files changed, 148 insertions(+), 132 deletions(-)
New commits:
commit 819b4015349b5d8c5ffa5f979097599774fce5bb
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Mar 15 13:47:29 2010 -0400
dump version for rc release
diff --git a/configure.ac b/configure.ac
index d2c70f5..c1fae22 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-ati],
- 6.12.191,
+ 6.12.192,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-ati)
commit d3482a947e3731be4ed0b00b4e3079470700dc4c
Author: Michael Cree <mcree@orcon.net.nz>
Date: Fri Mar 12 22:23:31 2010 +1300
Fix some word accesses in AtomBios to work on all architectures.
The UINT16LE_TO_CPU(), etc., macros are used in the AtomBios code to
fix up endian issues but they do not address bad alignment or assist
architectures that cannot perform hardware byte or word accesses.
This patch inserts use of the ldw_u(), etc., interface of the Xserver
into certain AtomBios accesses to address alignment issues.
This resolves Debian bug 572311, namely that the driver when compiled
for generic Alpha architecture (i.e. doesn't use the byte-word extension)
resulted in no display output on certain Radeon cards.
Signed-off-by: Michael Cree <mcree@orcon.net.nz>
diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c
index c1279b8..ae27049 100644
--- a/src/AtomBios/CD_Operations.c
+++ b/src/AtomBios/CD_Operations.c
@@ -42,6 +42,7 @@ Revision History:
#include <X11/Xos.h>
#include "xorg-server.h"
+#include "compiler.h"
#include "Decoder.h"
@@ -230,7 +231,7 @@ UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].func(pParserTempData);
pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
}
- pParserTempData->IndirectIOTablePointer-=UINT16LE_TO_CPU(*(UINT16*)(pParserTempData->IndirectIOTablePointer+1));
+ pParserTempData->IndirectIOTablePointer-=UINT16LE_TO_CPU(ldw_u((uint16_t *)(pParserTempData->IndirectIOTablePointer+1)));
pParserTempData->IndirectIOTablePointer++;
return pParserTempData->IndirectData;
} else pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
@@ -267,8 +268,8 @@ VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)=
- CPU_TO_UINT32LE(pParserTempData->DestData32);
+ stl_u(CPU_TO_UINT32LE(pParserTempData->DestData32),
+ pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination);
}
VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
@@ -341,7 +342,7 @@ VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
+ pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
pParserTempData->Index+=pParserTempData->CurrentRegBlock;
switch(pParserTempData->Multipurpose.CurrentPort)
@@ -425,9 +426,9 @@ UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- UINT32 ret;
+ UINT32 ret;
- pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
+ pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
ret = UINT32LE_TO_CPU(*(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock));
return ret;
@@ -444,7 +445,7 @@ UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->CD_Mask.SrcAlignment=alignmentLowerWord;
- pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
+ pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
return pParserTempData->Index;
}
@@ -680,7 +681,7 @@ VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
- while ( UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP) != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE))
+ while ( UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP)) != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE))
{
if (*pParserTempData->pWorkingTableData->IP == 'c')
{
commit 488c9fd8300505cc6c0c2f8f0f00849f27cc5d63
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Mar 15 12:25:57 2010 -0400
r6xx/r7xx: fix domain handling in accel code
Noticed by Pauli and Michel on IRC.
Improves GetImage performace by a factor of ~10.
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 488291d..0d7e9f9 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -276,7 +276,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
- vs_setup (pScrn, accel_state->ib, &vs_conf);
+ vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
/* flush SQ cache */
cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
@@ -290,7 +290,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
- ps_setup (pScrn, accel_state->ib, &ps_conf);
+ ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
/* Render setup */
if (pm & 0x000000ff)
@@ -324,7 +324,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
- set_render_target(pScrn, accel_state->ib, &cb_conf);
+ set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM);
/* Interpolator setup */
/* one unused export from VS (VS_EXPORT_COUNT is zero based, count minus one) */
@@ -498,7 +498,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
- vs_setup (pScrn, accel_state->ib, &vs_conf);
+ vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
/* flush SQ cache */
cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
@@ -512,12 +512,12 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
- ps_setup (pScrn, accel_state->ib, &ps_conf);
+ ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
/* flush texture cache */
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
accel_state->src_size[0], accel_state->src_mc_addr[0],
- accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
/* Texture */
tex_res.id = 0;
@@ -554,7 +554,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
tex_samp.id = 0;
tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL;
@@ -598,7 +598,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
- set_render_target(pScrn, accel_state->ib, &cb_conf);
+ set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* Interpolator setup */
/* export tex coord from VS */
@@ -1281,7 +1281,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
/* flush texture cache */
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
accel_state->src_size[unit], accel_state->src_mc_addr[unit],
- accel_state->src_bo[unit], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[unit], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
/* Texture */
tex_res.id = unit;
@@ -1414,7 +1414,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
tex_samp.id = unit;
tex_samp.border_color = SQ_TEX_BORDER_COLOR_TRANS_BLACK;
@@ -1715,7 +1715,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
vs_conf.num_gprs = 3;
vs_conf.stack_size = 1;
vs_conf.bo = accel_state->shaders_bo;
- vs_setup (pScrn, accel_state->ib, &vs_conf);
+ vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
/* flush SQ cache */
cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
@@ -1729,7 +1729,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
- ps_setup (pScrn, accel_state->ib, &ps_conf);
+ ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
BEGIN_BATCH(9);
EREG(accel_state->ib, CB_TARGET_MASK, (0xf << TARGET0_ENABLE_shift));
@@ -1782,7 +1782,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
- set_render_target(pScrn, accel_state->ib, &cb_conf);
+ set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM);
/* Interpolator setup */
BEGIN_BATCH(21);
diff --git a/src/r600_state.h b/src/r600_state.h
index 0ee480b..1f2fbaa 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -281,26 +281,26 @@ wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib);
void
start_3d(ScrnInfoPtr pScrn, drmBufPtr ib);
void
-set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf);
+set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain);
void
cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_t size, uint64_t mc_addr,
struct radeon_bo *bo, uint32_t rdomains, uint32_t wdomain);
void
cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
void
-fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf);
+fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain);
void
-vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf);
+vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain);
void
-ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf);
+ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain);
void
set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf);
void
set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val);
void
-set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res);
+set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t domain);
void
-set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res);
+set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain);
void
set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s);
void
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index f9b3a90..7b55cec 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -257,7 +257,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
- vs_setup (pScrn, accel_state->ib, &vs_conf);
+ vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
/* flush SQ cache */
cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
@@ -271,7 +271,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
- ps_setup (pScrn, accel_state->ib, &ps_conf);
+ ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
/* PS alu constants */
set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps,
@@ -286,7 +286,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* flush texture cache */
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, accel_state->src_size[0],
accel_state->src_mc_addr[0],
- accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
/* Y texture */
tex_res.id = 0;
@@ -311,7 +311,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
tex_res.interlaced = 0;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* Y sampler */
tex_samp.id = 0;
@@ -331,7 +331,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
accel_state->src_size[0] / 4,
accel_state->src_mc_addr[0] + pPriv->planev_offset,
- accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
tex_res.id = 1;
tex_res.format = FMT_8;
@@ -346,7 +346,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_mc_addr[0] + pPriv->planev_offset;
tex_res.mip_base = accel_state->src_mc_addr[0] + pPriv->planev_offset;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* U or V sampler */
tex_samp.id = 1;
@@ -356,7 +356,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
accel_state->src_size[0] / 4,
accel_state->src_mc_addr[0] + pPriv->planeu_offset,
- accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
tex_res.id = 2;
tex_res.format = FMT_8;
@@ -371,7 +371,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_mc_addr[0] + pPriv->planeu_offset;
tex_res.mip_base = accel_state->src_mc_addr[0] + pPriv->planeu_offset;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* UV sampler */
tex_samp.id = 2;
@@ -385,7 +385,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* flush texture cache */
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, accel_state->src_size[0],
accel_state->src_mc_addr[0],
- accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
/* Y texture */
tex_res.id = 0;
@@ -413,7 +413,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
tex_res.interlaced = 0;
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* Y sampler */
tex_samp.id = 0;
@@ -448,7 +448,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_mc_addr[0];
tex_res.mip_base = accel_state->src_mc_addr[0];
- set_tex_resource (pScrn, accel_state->ib, &tex_res);
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
/* UV sampler */
tex_samp.id = 1;
@@ -488,7 +488,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
- set_render_target(pScrn, accel_state->ib, &cb_conf);
+ set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM);
/* Interpolator setup */
/* export tex coords from VS */
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 3ec9018..d7a95a4 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -222,7 +222,7 @@ sq_setup(ScrnInfoPtr pScrn, drmBufPtr ib, sq_config_t *sq_conf)
}
void
-set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf)
+set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain)
{
uint32_t cb_color_info;
int pitch, slice, h;
@@ -259,7 +259,7 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf)
BEGIN_BATCH(3 + 2);
EREG(ib, (CB_COLOR0_BASE + (4 * cb_conf->id)), (cb_conf->base >> 8));
- RELOC_BATCH(cb_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(cb_conf->bo, 0, domain);
END_BATCH();
// rv6xx workaround
@@ -276,11 +276,11 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf)
*/
BEGIN_BATCH(3 + 2);
EREG(ib, (CB_COLOR0_TILE + (4 * cb_conf->id)), (0 >> 8)); // CMASK per-tile data base/256
- RELOC_BATCH(cb_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(cb_conf->bo, 0, domain);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(ib, (CB_COLOR0_FRAG + (4 * cb_conf->id)), (0 >> 8)); // FMASK per-tile data base/256
- RELOC_BATCH(cb_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(cb_conf->bo, 0, domain);
END_BATCH();
BEGIN_BATCH(12);
// pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib
@@ -399,7 +399,7 @@ void cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
}
void
-fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf)
+fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_pgm_resources;
@@ -412,7 +412,7 @@ fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf)
BEGIN_BATCH(3 + 2);
EREG(ib, SQ_PGM_START_FS, fs_conf->shader_addr >> 8);
- RELOC_BATCH(fs_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(fs_conf->bo, domain, 0);
END_BATCH();
BEGIN_BATCH(6);
@@ -422,7 +422,7 @@ fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf)
}
void
-vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf)
+vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_pgm_resources;
@@ -439,7 +439,7 @@ vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf)
BEGIN_BATCH(3 + 2);
EREG(ib, SQ_PGM_START_VS, vs_conf->shader_addr >> 8);
- RELOC_BATCH(vs_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(vs_conf->bo, domain, 0);
END_BATCH();
BEGIN_BATCH(6);
@@ -449,7 +449,7 @@ vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf)
}
void
-ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf)
+ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_pgm_resources;
@@ -468,7 +468,7 @@ ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf)
BEGIN_BATCH(3 + 2);
EREG(ib, SQ_PGM_START_PS, ps_conf->shader_addr >> 8);
- RELOC_BATCH(ps_conf->bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(ps_conf->bo, domain, 0);
END_BATCH();
BEGIN_BATCH(9);
@@ -505,7 +505,7 @@ set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val)
}
void
-set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res)
+set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_vtx_constant_word2;
@@ -533,12 +533,12 @@ set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res)
E32(ib, 0); // 4: n/a
E32(ib, 0); // 5: n/a
E32(ib, SQ_TEX_VTX_VALID_BUFFER << SQ_VTX_CONSTANT_WORD6_0__TYPE_shift); // 6: TYPE
- RELOC_BATCH(res->bo, RADEON_GEM_DOMAIN_GTT, 0);
+ RELOC_BATCH(res->bo, domain, 0);
END_BATCH();
}
void
-set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res)
+set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
@@ -599,8 +599,8 @@ set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res)
E32(ib, sq_tex_resource_word4);
E32(ib, sq_tex_resource_word5);
E32(ib, sq_tex_resource_word6);
- RELOC_BATCH(tex_res->bo, RADEON_GEM_DOMAIN_VRAM, 0);
- RELOC_BATCH(tex_res->mip_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ RELOC_BATCH(tex_res->bo, domain, 0);
+ RELOC_BATCH(tex_res->mip_bo, domain, 0);
END_BATCH();
}
@@ -1085,7 +1085,7 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
// clear FS
fs_conf.bo = accel_state->shaders_bo;
- fs_setup(pScrn, ib, &fs_conf);
+ fs_setup(pScrn, ib, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
// VGT
BEGIN_BATCH(75);
@@ -1271,7 +1271,7 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
vtx_res.mem_req_size = 1;
vtx_res.vb_addr = accel_state->vb_mc_addr + accel_state->vb_start_op;
vtx_res.bo = accel_state->vb_bo;
- set_vtx_resource (pScrn, accel_state->ib, &vtx_res);
+ set_vtx_resource (pScrn, accel_state->ib, &vtx_res, RADEON_GEM_DOMAIN_GTT);
/* Draw */
draw_conf.prim_type = DI_PT_RECTLIST;
@@ -1288,7 +1288,7 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
/* sync dst surface */
cp_set_surface_sync(pScrn, accel_state->ib, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit),
accel_state->dst_size, accel_state->dst_mc_addr,
- accel_state->dst_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->dst_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
accel_state->vb_start_op = -1;
accel_state->ib_reset_op = 0;
commit 2ace2591d92fb6d3ce7a6453edb04b36a6c49a32
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Mar 15 12:03:58 2010 -0400
radeon: remove some leftover debugging output
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 4ed1c69..b627637 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -2866,8 +2866,6 @@ static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn)
else
mask = 3;
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "mask: %d\n", mask);
-
if (!RADEONAllocateControllers(pScrn, mask))
return FALSE;
commit 67e81c8f17ddde6eba633d2a5aef528e1d598d89
Author: Andrzej Hajda <andrzej.hajda@wp.pl>
Date: Wed Mar 10 18:19:35 2010 -0500
radeon: add support for pal on legacy IGP chips
Based on my initial non-working patch.
Fixes some element of fdo bug 12007
diff --git a/src/radeon_tv.c b/src/radeon_tv.c
index 6c083ce..74c82db 100644
--- a/src/radeon_tv.c
+++ b/src/radeon_tv.c
@@ -186,6 +186,21 @@ static const TVModeConstants availableTVModes[] =
8, /* crtcPLL_postDiv */
1022, /* pixToTV */
},
+ { /* PAL timing for 14 Mhz ref clk */
+ 800, /* horResolution */
+ 600, /* verResolution */
+ TV_STD_PAL, /* standard */
+ 1131, /* horTotal */
+ 742, /* verTotal */
+ 813, /* horStart */
+ 840, /* horSyncStart */
+ 633, /* verSyncStart */
+ 708369, /* defRestart */
+ 211, /* crtcPLL_N */
+ 9, /* crtcPLL_M */
+ 8, /* crtcPLL_postDiv */
+ 759, /* pixToTV */
+ },
};
#define N_AVAILABLE_MODES (sizeof(availableModes) / sizeof(availableModes[ 0 ]))
@@ -625,7 +640,7 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
hTotal = constPtr->horTotal;
@@ -754,7 +769,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->tv_crc_cntl = 0;
@@ -939,10 +954,9 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
n = PAL_TV_PLL_N_27;
p = PAL_TV_PLL_P_27;
} else {
- /* FIXME */
- m = PAL_TV_PLL_M_27;
- n = PAL_TV_PLL_N_27;
- p = PAL_TV_PLL_P_27;
+ m = PAL_TV_PLL_M_14;
+ n = PAL_TV_PLL_N_14;
+ p = PAL_TV_PLL_P_14;
}
}
save->tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) |
@@ -1080,7 +1094,7 @@ void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->crtc_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
@@ -1121,7 +1135,7 @@ void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->htotal_cntl = (constPtr->horTotal & 0x7 /*0xf*/) | RADEON_HTOT_CNTL_VGA_EN;
@@ -1184,7 +1198,7 @@ void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->crtc2_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
@@ -1225,7 +1239,7 @@ void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->htotal_cntl2 = (constPtr->horTotal & 0x7); /* 0xf */
diff --git a/src/radeon_tv.h b/src/radeon_tv.h
index 8d77a77..719452d 100644
--- a/src/radeon_tv.h
+++ b/src/radeon_tv.h
@@ -53,6 +53,10 @@
#define NTSC_TV_PLL_N_14 693
#define NTSC_TV_PLL_P_14 7
+#define PAL_TV_PLL_M_14 19
+#define PAL_TV_PLL_N_14 353
+#define PAL_TV_PLL_P_14 5
+
#define VERT_LEAD_IN_LINES 2
#define FRAC_BITS 0xe
#define FRAC_MASK 0x3fff
commit 3a44f1cb0d2bb748692b1024003de8ee88ca77a5
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Tue Mar 9 09:44:01 2010 -0500
atom: i2c gpio fixes
Basically a port of my kms patch. This allows us
to remove some quirks.
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 0fa53ff..bbe3d8e 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1515,9 +1515,10 @@ RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id)
{
RADEONInfoPtr info = RADEONPTR (pScrn);
atomDataTablesPtr atomDataPtr;
- ATOM_GPIO_I2C_ASSIGMENT gpio;
+ ATOM_GPIO_I2C_ASSIGMENT *gpio;
RADEONI2CBusRec i2c;
uint8_t crev, frev;
+ int i;
memset(&i2c, 0, sizeof(RADEONI2CBusRec));
i2c.valid = FALSE;
@@ -1531,48 +1532,53 @@ RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id)
return i2c;
}
- gpio = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[id];
- i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
- i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
- i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
- i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
- i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
- i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
- i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
- i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
- i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
- i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
- i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
- i2c.put_data_mask = (1 << gpio.ucDataEnShift);
- i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
- i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
- i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
- i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
- i2c.hw_line = gpio.sucI2cId.sbfAccess.bfI2C_LineMux;
- i2c.hw_capable = gpio.sucI2cId.sbfAccess.bfHW_Capable;
- i2c.valid = TRUE;
+ for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
+ gpio = &atomDataPtr->GPIO_I2C_Info->asGPIO_Info[i];
+ if (gpio->sucI2cId.ucAccess == id) {
+ i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
+ i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
+ i2c.put_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
+ i2c.put_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
+ i2c.get_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
+ i2c.get_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
+ i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
+ i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
+ i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
+ i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
+ i2c.put_clk_mask = (1 << gpio->ucClkEnShift);
+ i2c.put_data_mask = (1 << gpio->ucDataEnShift);
+ i2c.get_clk_mask = (1 << gpio->ucClkY_Shift);
+ i2c.get_data_mask = (1 << gpio->ucDataY_Shift);
+ i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
+ i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
+ i2c.hw_line = gpio->sucI2cId.ucAccess;
+ i2c.hw_capable = gpio->sucI2cId.sbfAccess.bfHW_Capable;
+ i2c.valid = TRUE;
+ break;
+ }
+ }
#if 0
ErrorF("id: %d\n", id);
- ErrorF("hw capable: %d\n", gpio.sucI2cId.sbfAccess.bfHW_Capable);
- ErrorF("hw engine id: %d\n", gpio.sucI2cId.sbfAccess.bfHW_EngineID);
- ErrorF("line mux %d\n", gpio.sucI2cId.sbfAccess.bfI2C_LineMux);
- ErrorF("mask_clk_reg: 0x%x\n", gpio.usClkMaskRegisterIndex * 4);
- ErrorF("mask_data_reg: 0x%x\n", gpio.usDataMaskRegisterIndex * 4);
- ErrorF("put_clk_reg: 0x%x\n", gpio.usClkEnRegisterIndex * 4);
- ErrorF("put_data_reg: 0x%x\n", gpio.usDataEnRegisterIndex * 4);
- ErrorF("get_clk_reg: 0x%x\n", gpio.usClkY_RegisterIndex * 4);
- ErrorF("get_data_reg: 0x%x\n", gpio.usDataY_RegisterIndex * 4);
- ErrorF("a_clk_reg: 0x%x\n", gpio.usClkA_RegisterIndex * 4);
- ErrorF("a_data_reg: 0x%x\n", gpio.usDataA_RegisterIndex * 4);
- ErrorF("mask_clk_mask: %d\n", gpio.ucClkMaskShift);
- ErrorF("mask_data_mask: %d\n", gpio.ucDataMaskShift);
- ErrorF("put_clk_mask: %d\n", gpio.ucClkEnShift);
- ErrorF("put_data_mask: %d\n", gpio.ucDataEnShift);
- ErrorF("get_clk_mask: %d\n", gpio.ucClkY_Shift);
- ErrorF("get_data_mask: %d\n", gpio.ucDataY_Shift);
- ErrorF("a_clk_mask: %d\n", gpio.ucClkA_Shift);
- ErrorF("a_data_mask: %d\n", gpio.ucDataA_Shift);
+ ErrorF("hw capable: %d\n", gpio->sucI2cId.sbfAccess.bfHW_Capable);
+ ErrorF("hw engine id: %d\n", gpio->sucI2cId.sbfAccess.bfHW_EngineID);
+ ErrorF("line mux %d\n", gpio->sucI2cId.sbfAccess.bfI2C_LineMux);
+ ErrorF("mask_clk_reg: 0x%x\n", gpio->usClkMaskRegisterIndex * 4);
+ ErrorF("mask_data_reg: 0x%x\n", gpio->usDataMaskRegisterIndex * 4);
+ ErrorF("put_clk_reg: 0x%x\n", gpio->usClkEnRegisterIndex * 4);
+ ErrorF("put_data_reg: 0x%x\n", gpio->usDataEnRegisterIndex * 4);
+ ErrorF("get_clk_reg: 0x%x\n", gpio->usClkY_RegisterIndex * 4);
+ ErrorF("get_data_reg: 0x%x\n", gpio->usDataY_RegisterIndex * 4);
+ ErrorF("a_clk_reg: 0x%x\n", gpio->usClkA_RegisterIndex * 4);
+ ErrorF("a_data_reg: 0x%x\n", gpio->usDataA_RegisterIndex * 4);
+ ErrorF("mask_clk_mask: %d\n", gpio->ucClkMaskShift);
+ ErrorF("mask_data_mask: %d\n", gpio->ucDataMaskShift);
+ ErrorF("put_clk_mask: %d\n", gpio->ucClkEnShift);
+ ErrorF("put_data_mask: %d\n", gpio->ucDataEnShift);
+ ErrorF("get_clk_mask: %d\n", gpio->ucClkY_Shift);
+ ErrorF("get_data_mask: %d\n", gpio->ucDataY_Shift);
+ ErrorF("a_clk_mask: %d\n", gpio->ucClkA_Shift);
+ ErrorF("a_data_mask: %d\n", gpio->ucDataA_Shift);
#endif
return i2c;
@@ -1585,9 +1591,9 @@ rhdAtomParseI2CRecord(ScrnInfoPtr pScrn, atomBiosHandlePtr handle,
RADEONInfoPtr info = RADEONPTR (pScrn);
uint8_t *temp = &Record->sucI2cId;
- info->BiosConnector[i].i2c_line_mux = Record->sucI2cId.bfI2C_LineMux;
+ info->BiosConnector[i].i2c_line_mux = *temp;
info->BiosConnector[i].ucI2cId = *temp;
- return RADEONLookupGPIOLineForDDC(pScrn, Record->sucI2cId.bfI2C_LineMux);
+ return RADEONLookupGPIOLineForDDC(pScrn, *temp);
}
static uint8_t
@@ -2518,7 +2524,7 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
info->BiosConnector[i].valid = TRUE;
info->BiosConnector[i].load_detection = TRUE;
info->BiosConnector[i].shared_ddc = FALSE;
- info->BiosConnector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux;
+ info->BiosConnector[i].output_id = ci.sucI2cId.ucAccess;
info->BiosConnector[i].devices = (1 << i);
info->BiosConnector[i].ConnectorType = ci.sucConnectorInfo.sbfAccess.bfConnectorType;
@@ -2532,21 +2538,9 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
(i == ATOM_DEVICE_TV2_INDEX) ||
(i == ATOM_DEVICE_CV_INDEX))
info->BiosConnector[i].ddc_i2c.valid = FALSE;
- else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
- (info->ChipFamily == CHIP_FAMILY_RS740)) {
- /* IGP DFP ports sometimes use non-standard gpio entries */
- if ((i == ATOM_DEVICE_DFP2_INDEX) && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
- info->BiosConnector[i].ddc_i2c =
- RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1);
- else if ((i == ATOM_DEVICE_DFP3_INDEX) && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
- info->BiosConnector[i].ddc_i2c =
- RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1);
- else
- info->BiosConnector[i].ddc_i2c =
- RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
- } else
+ else
info->BiosConnector[i].ddc_i2c =
- RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
+ RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.ucAccess);
if (!radeon_add_encoder(pScrn,
radeon_get_encoder_id_from_supported_device(pScrn, (1 << i),
commit d85cb40f516c67305e818302bec7ee817df4144c
Author: Matt Turner <mattst88@gmail.com>
Date: Sun Mar 7 14:24:35 2010 -0500
Don't check for Xinerama.
It doesn't seem to be used anywhere, so don't require it.
CC: Jerome Glisse <jglisse@redhat.com>
CC: Alex Deucher <alexdeucher@gmail.com>
CC: Dave Airlie <airlied@redhat.com>
Signed-off-by: Matt Turner <mattst88@gmail.com>
diff --git a/configure.ac b/configure.ac
index 058535c..d2c70f5 100644
--- a/configure.ac
+++ b/configure.ac
@@ -82,7 +82,6 @@ AC_ARG_WITH(xserver-source,AC_HELP_STRING([--with-xserver-source=XSERVER_SOURCE]
[ XSERVER_SOURCE="" ])
# Checks for extensions
-XORG_DRIVER_CHECK_EXT(XINERAMA, xineramaproto)
XORG_DRIVER_CHECK_EXT(RANDR, randrproto)
XORG_DRIVER_CHECK_EXT(RENDER, renderproto)
XORG_DRIVER_CHECK_EXT(XV, videoproto)
commit e7b41f8cb082ed462d29bf3fc440072424cbd852
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Fri Mar 5 19:16:11 2010 -0500
radeon: disable frac fb div with new pll code
fixes fdo bug 26897
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 0635c91..0b071b8 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -461,8 +461,8 @@ RADEONComputePLL(ScrnInfoPtr pScrn,
if (IS_AVIVO_VARIANT) {
if (xf86ReturnOptValBool(info->Options, OPTION_NEW_PLL, TRUE)) {
- /* to match previous behavior */
- flags |= RADEON_PLL_USE_FRAC_FB_DIV;
+ /* disable frac fb dividers */
+ flags &= ~RADEON_PLL_USE_FRAC_FB_DIV;
RADEONComputePLL_new(pll, freq, chosen_dot_clock_freq,
chosen_feedback_div, chosen_frac_feedback_div,
chosen_reference_div, chosen_post_div, flags);
commit 14aff767490c253cbcdd411f812e50b91673119e
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Wed Mar 3 13:31:19 2010 -0500
radeon: add new RS880 pci id
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index 3dd36da..f88b069 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -453,6 +453,7 @@
#define PCI_CHIP_RS880_9712 0x9712
#define PCI_CHIP_RS880_9713 0x9713
#define PCI_CHIP_RS880_9714 0x9714
+#define PCI_CHIP_RS880_9715 0x9715
#define PCI_CHIP_CYPRESS_6880 0x6880
#define PCI_CHIP_CYPRESS_6888 0x6888
#define PCI_CHIP_CYPRESS_6889 0x6889
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 9c72c40..b26cf25 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -453,7 +453,8 @@
"0x9711","RS880_9711","RS880",,1,,,1,"ATI Radeon 4100"
"0x9712","RS880_9712","RS880",1,1,,,1,"ATI Mobility Radeon HD 4200"
"0x9713","RS880_9713","RS880",1,1,,,1,"ATI Mobility Radeon 4100"
-"0x9714","RS880_9714","RS880",,1,,,1,"ATI RS880"
+"0x9714","RS880_9714","RS880",,1,,,1,"ATI Radeon HD 4290"
+"0x9715","RS880_9715","RS880",,1,,,1,"ATI Radeon HD 4290"
"0x6880","CYPRESS_6880","CYPRESS",1,,,,,"CYPRESS"
"0x6888","CYPRESS_6888","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
"0x6889","CYPRESS_6889","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index bdbd358..0f53790 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -373,6 +373,7 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x9712, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 },
{ 0x9713, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 },
{ 0x9714, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 },
+ { 0x9715, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 },
{ 0x6880, CHIP_FAMILY_CYPRESS, 1, 0, 0, 0, 0 },
{ 0x6888, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
{ 0x6889, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index da0d3b4..7b74d7e 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -372,7 +372,8 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RS880_9711, "ATI Radeon 4100" },
{ PCI_CHIP_RS880_9712, "ATI Mobility Radeon HD 4200" },
{ PCI_CHIP_RS880_9713, "ATI Mobility Radeon 4100" },
- { PCI_CHIP_RS880_9714, "ATI RS880" },
+ { PCI_CHIP_RS880_9714, "ATI Radeon HD 4290" },
+ { PCI_CHIP_RS880_9715, "ATI Radeon HD 4290" },
{ PCI_CHIP_CYPRESS_6880, "CYPRESS" },
{ PCI_CHIP_CYPRESS_6888, "ATI FirePro (FireGL) Graphics Adapter" },
{ PCI_CHIP_CYPRESS_6889, "ATI FirePro (FireGL) Graphics Adapter" },
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index 1f1b97e..8afa10d 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -373,6 +373,7 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RS880_9712, PCI_CHIP_RS880_9712, RES_SHARED_VGA },
{ PCI_CHIP_RS880_9713, PCI_CHIP_RS880_9713, RES_SHARED_VGA },
{ PCI_CHIP_RS880_9714, PCI_CHIP_RS880_9714, RES_SHARED_VGA },
+ { PCI_CHIP_RS880_9715, PCI_CHIP_RS880_9715, RES_SHARED_VGA },
{ PCI_CHIP_CYPRESS_6880, PCI_CHIP_CYPRESS_6880, RES_SHARED_VGA },
{ PCI_CHIP_CYPRESS_6888, PCI_CHIP_CYPRESS_6888, RES_SHARED_VGA },
{ PCI_CHIP_CYPRESS_6889, PCI_CHIP_CYPRESS_6889, RES_SHARED_VGA },
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
index fa44875..a09c969 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -373,6 +373,7 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9712, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9713, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9714, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RS880_9715, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6880, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6888, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6889, 0 ),
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