xserver-xorg-video-radeonhd: Changes to 'upstream-unstable'
Makefile.am | 2
README | 14
configure.ac | 3
man/radeonhd.man | 124 -
src/Makefile.am | 9
src/r5xx_accel.c | 9
src/r5xx_accel.h | 2
src/r5xx_exa.c | 12
src/r5xx_xaa.c | 2
src/r600_exa.c | 2150 ++++++++++++++++++++++++++++
src/r600_reg.h | 140 +
src/r600_reg_auto_r6xx.h | 3087 +++++++++++++++++++++++++++++++++++++++++
src/r600_reg_r6xx.h | 504 ++++++
src/r600_reg_r7xx.h | 149 +
src/r600_shader.c | 1848 ++++++++++++++++++++++++
src/r600_shader.h | 359 ++++
src/r600_state.h | 293 +++
src/r600_textured_videofuncs.c | 531 +++++++
src/r6xx_accel.c | 1233 ++++++++++++++++
src/r6xx_accel.h | 89 +
src/radeon_exa_render.c | 2
src/rhd.h | 49
src/rhd_atombios.c | 4
src/rhd_atombios.h | 2
src/rhd_atomcrtc.c | 15
src/rhd_atomout.c | 152 +-
src/rhd_atomout.h | 2
src/rhd_atompll.c | 2
src/rhd_atomwrapper.c | 2
src/rhd_atomwrapper.h | 2
src/rhd_audio.c | 4
src/rhd_audio.h | 2
src/rhd_biosscratch.c | 2
src/rhd_biosscratch.h | 2
src/rhd_card.h | 2
src/rhd_connector.c | 2
src/rhd_connector.h | 2
src/rhd_crtc.c | 47
src/rhd_crtc.h | 4
src/rhd_cs.c | 27
src/rhd_cs.h | 2
src/rhd_cursor.c | 10
src/rhd_cursor.h | 2
src/rhd_dac.c | 2
src/rhd_ddia.c | 2
src/rhd_dig.c | 208 +-
src/rhd_dri.c | 171 +-
src/rhd_dri.h | 2
src/rhd_driver.c | 215 +-
src/rhd_edid.c | 2
src/rhd_hdmi.c | 2
src/rhd_hdmi.h | 2
src/rhd_helper.c | 32
src/rhd_i2c.c | 16
src/rhd_i2c.h | 2
src/rhd_id.c | 68
src/rhd_lut.c | 77 -
src/rhd_lut.h | 2
src/rhd_lvtma.c | 75
src/rhd_mc.c | 948 +++++-------
src/rhd_mc.h | 16
src/rhd_modes.c | 2
src/rhd_modes.h | 2
src/rhd_monitor.c | 2
src/rhd_monitor.h | 2
src/rhd_output.c | 58
src/rhd_output.h | 6
src/rhd_pll.c | 2
src/rhd_pll.h | 2
src/rhd_randr.c | 293 ++-
src/rhd_randr.h | 2
src/rhd_regs.h | 6
src/rhd_shadow.c | 2
src/rhd_shadow.h | 2
src/rhd_tmds.c | 57
src/rhd_vga.c | 133 +
src/rhd_vga.h | 21
src/rhd_video.c | 223 ++
src/rhd_video.h | 12
utils/conntest/rhd_conntest.c | 2
utils/conntest/rhd_dump.c | 38
81 files changed, 12274 insertions(+), 1335 deletions(-)
New commits:
commit cb54f48b212d5ae54e13bbdf24575b6163798c0d
Author: Matthias Hopf <mhopf@suse.de>
Date: Thu Apr 9 15:11:37 2009 +0200
Bump to 1.2.5. Updated README.
diff --git a/README b/README
index a6f311a..6ca6b20 100644
--- a/README
+++ b/README
@@ -87,6 +87,18 @@ Major Changes
Read ChangeLog for a complete list.
+- Version 1.2.5
+
+ - Added 2D acceleration for R6xx and R7xx.
+ - Added XVideo support for R6xx and R7xx.
+ - Added support for RS880 and RV790.
+ - Added RandR 1.3 mandatory properties.
+ - Refactoring of MC code.
+ - Enable DRI support by default on R5xx and RS6xx.
+ - LUT (color lookup table) fixes.
+ - Tons of quirk table entries and bug fixes.
+ - Fix register accesses for processors that reorder memory writes.
+
- Version 1.2.4
- Added HDMI support.
diff --git a/configure.ac b/configure.ac
index fbbc5b7..c31f10a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2,7 +2,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-radeonhd],
- 1.2.4,
+ 1.2.5,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/radeonhd],
xf86-video-radeonhd)
commit 9d2a508892f16572127d192497bcf505556538b8
Author: Yang Zhao <yang@yangman.ca>
Date: Thu Apr 9 15:01:05 2009 +0200
Fix resume from suspend for r6xx/r7xx
Move DRM calls to DRM_RADEON_CP_RESUME and RADEON_SETPARAM_VBLANK_CRTC
to after doing GART backup. Also move call to DRIUnlock() to end of
RHDEnterVT() from RHDDRIEnterVT().
diff --git a/src/rhd_dri.c b/src/rhd_dri.c
index 1aa50f6..d06ba43 100644
--- a/src/rhd_dri.c
+++ b/src/rhd_dri.c
@@ -1629,10 +1629,6 @@ void RHDDRIEnterVT(ScreenPtr pScreen)
RHDSetAgpBase(rhdDRI, pScreen);
}
- if ( (ret = drmCommandNone(rhdDRI->drmFD, DRM_RADEON_CP_RESUME)) )
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "%s: CP resume %d\n", __func__, ret);
-
/* TODO: maybe using CP_INIT instead of CP_RESUME is enough, so we wouldn't
* need an additional copy of the GART table in main memory. OTOH the table
* must be initialized but not allocated anew. */
@@ -1643,7 +1639,9 @@ void RHDDRIEnterVT(ScreenPtr pScreen)
RHDDRISetVBlankInterrupt(pScrn, rhdDRI->have3Dwindows);
- DRIUnlock(pScrn->pScreen);
+ if ( (ret = drmCommandNone(rhdDRI->drmFD, DRM_RADEON_CP_RESUME)) )
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "%s: CP resume %d\n", __func__, ret);
}
/* Stop all before vt switch / suspend */
diff --git a/src/rhd_driver.c b/src/rhd_driver.c
index f7edb4a..f849faa 100644
--- a/src/rhd_driver.c
+++ b/src/rhd_driver.c
@@ -1448,6 +1448,12 @@ RHDEnterVT(int scrnIndex, int flags)
RHDCSIdle(rhdPtr->CS);
}
+#ifdef USE_DRI
+ if (rhdPtr->dri) {
+ DRIUnlock(pScrn->pScreen);
+ }
+#endif
+
return TRUE;
}
commit 1137e0963e322dcb41816bdc76c57d3e3d407166
Author: Matthias Hopf <mhopf@suse.de>
Date: Thu Apr 9 11:42:35 2009 +0200
RHDDRIGetIntGARTLocation is called too often to be logged. Nuked RHDFUNC there.
diff --git a/src/rhd_dri.c b/src/rhd_dri.c
index 89bd676..1aa50f6 100644
--- a/src/rhd_dri.c
+++ b/src/rhd_dri.c
@@ -2003,8 +2003,6 @@ RHDDRIGetIntGARTLocation(ScrnInfoPtr pScrn)
RHDPtr rhdPtr = RHDPTR(pScrn);
struct rhdDri *rhdDRI = rhdPtr->dri;
- RHDFUNC(rhdPtr);
-
if (!rhdDRI->gartLocation)
return 0;
commit 76d6973a5c18b5aff7e7027a2f87d3616179e2e9
Author: Matthias Hopf <mhopf@suse.de>
Date: Wed Apr 8 17:01:49 2009 +0200
man: R6xx and R7xx 2D possible now.
diff --git a/man/radeonhd.man b/man/radeonhd.man
index a363e24..e7a4d99 100644
--- a/man/radeonhd.man
+++ b/man/radeonhd.man
@@ -30,9 +30,7 @@ has the following limitations:
.\".TP "\w'\fB\(bu\fR'u+1n"
.TP 2
\(bu
-On R6xx and R7xx based cards:
-.B NO
-support for hardware-based 2D & 3D acceleration, no support for Xvideo.
+Support for hardware-based 2D acceleration and Xvideo needs more testing on R6xx and R7xx based cards.
.TP
\(bu
No TV and Component connector support so far.
commit 0065697647401fd4b0df13df94bd9ebedcac96dc
Author: Yang Zhao <yang@yangman.ca>
Date: Wed Mar 25 19:26:02 2009 -0700
LUT: reduce number of writes to DC_LUT_RW_INDEX
The value of DC_LUT_RW_INDEX is increased everytime DC_LUT_30_COLOR is
accessed. It is pointless to set this explicitly for each row of the
input colour table.
Signed-off-by: Yang Zhao <yang@yangman.ca>
diff --git a/src/rhd_lut.c b/src/rhd_lut.c
index 21c65d5..848ec13 100644
--- a/src/rhd_lut.c
+++ b/src/rhd_lut.c
@@ -32,6 +32,8 @@
#include "rhd_lut.h"
#include "rhd_regs.h"
+#include <compiler.h>
+
#define RHD_REGOFFSET_LUTA 0x000
#define RHD_REGOFFSET_LUTB 0x800
@@ -124,7 +126,7 @@ LUTxSet(struct rhdLUT *LUT, int numColors, int *indices, LOCO *colors)
{
ScrnInfoPtr pScrn = xf86Screens[LUT->scrnIndex];
CARD16 RegOff;
- int i, index;
+ int i, index, hw_index;
LUT->Initialised = TRUE; /* thank you RandR */
@@ -151,39 +153,64 @@ LUTxSet(struct rhdLUT *LUT, int numColors, int *indices, LOCO *colors)
RHDRegWrite(LUT, DC_LUT_RW_MODE, 0); /* table */
RHDRegWrite(LUT, DC_LUT_WRITE_EN_MASK, 0x0000003F);
+ /* DC_LUT_RW_INDEX is incremented automatically when DC_LUT_30_COLOR
+ * is accessed; hw_index is used to track the value of DC_LUT_RW_INDEX
+ * so that we can properly handle the very unlikely case that the input
+ * table indexes are not monotonically increasing
+ */
switch (pScrn->depth) {
case 8:
case 24:
case 32:
+ RHDRegWrite(LUT, DC_LUT_RW_INDEX, 0);
+ hw_index = 0;
for (i = 0; i < numColors; i++) {
- index = indices[i];
- RHDRegWrite(LUT, DC_LUT_RW_INDEX, index);
+ index = indices[i];
+ if (hw_index != index) {
+ RHDRegWrite(LUT, DC_LUT_RW_INDEX, index);
+ hw_index = index;
+ }
RHDRegWrite(LUT, DC_LUT_30_COLOR, (colors[index].red << 20) |
(colors[index].green << 10) | (colors[index].blue));
+ hw_index++;
}
break;
case 16:
+ RHDRegWrite(LUT, DC_LUT_RW_INDEX, 0);
+ hw_index = 0;
for (i = 0; i < numColors; i++) {
int j;
index = indices[i];
- RHDRegWrite(LUT, DC_LUT_RW_INDEX, 4 * index);
+ if (hw_index != 4 * index) {
+ RHDRegWrite(LUT, DC_LUT_RW_INDEX, 4 * index);
+ hw_index = 4 * index;
+ }
- for (j = 0; j < 4; j++)
+ for (j = 0; j < 4; j++) {
RHDRegWrite(LUT, DC_LUT_30_COLOR, (colors[index/2].red << 20) |
(colors[index].green << 10) | (colors[index/2].blue));
+ hw_index++;
+ }
}
break;
case 15:
+ RHDRegWrite(LUT, DC_LUT_RW_INDEX, 0);
+ hw_index = 0;
for (i = 0; i < numColors; i++) {
int j;
index = indices[i];
- RHDRegWrite(LUT, DC_LUT_RW_INDEX, 8 * index);
+ if (hw_index != 8 * index) {
+ RHDRegWrite(LUT, DC_LUT_RW_INDEX, 8 * index);
+ hw_index = 8 * index;
+ }
- for (j = 0; j < 8; j++)
+ for (j = 0; j < 8; j++) {
RHDRegWrite(LUT, DC_LUT_30_COLOR, (colors[index].red << 20) |
(colors[index].green << 10) | (colors[index].blue));
+ hw_index++;
+ }
}
break;
}
commit 6d7f2486ea5f7794dee0c8d8d2655ddad378eff5
Author: Matthias Hopf <mhopf@suse.de>
Date: Fri Apr 3 11:54:14 2009 +0200
Use () in macro arguments of new RHDRegMask.
diff --git a/src/rhd.h b/src/rhd.h
index b4edf37..e58689c 100644
--- a/src/rhd.h
+++ b/src/rhd.h
@@ -383,10 +383,10 @@ extern Bool RHDUseAtom(RHDPtr rhdPtr, enum RHD_CHIPSETS *BlackList, enum atomSub
#define RHDRegMask(ptr, offset, value, mask) \
do { \
CARD32 tmp; \
- tmp = RHDRegRead(ptr, offset); \
- tmp &= ~mask; \
- tmp |= (value & mask); \
- RHDRegWrite(ptr, offset, tmp); \
+ tmp = RHDRegRead((ptr), (offset)); \
+ tmp &= ~(mask); \
+ tmp |= ((value) & (mask)); \
+ RHDRegWrite((ptr), (offset), tmp); \
} while(0)
extern CARD32 _RHDReadMC(int scrnIndex, CARD32 addr);
commit d6c3727751a2de2c333e654aea1bd9b1d9c2ef44
Author: Yang Zhao <yang@yangman.ca>
Date: Fri Mar 27 21:21:25 2009 -0700
CS: Replace register read/write macros with ones from compiler.h
Signed-off-by: Yang Zhao <yang@yangman.ca>
diff --git a/src/rhd_cs.c b/src/rhd_cs.c
index b5f38a9..5e9fa02 100644
--- a/src/rhd_cs.c
+++ b/src/rhd_cs.c
@@ -31,6 +31,8 @@
#include "xf86.h"
+#include <compiler.h>
+
#include "rhd.h"
#include "rhd_cs.h"
#include "r5xx_regs.h"
@@ -50,8 +52,8 @@
/* First... provide some macro's for accessing the registers, which will
somewhat speed up things */
-#define CSMMIORegRead(Reg) (*(volatile CARD32 *) (MMIOBase + (Reg)))
-#define CSMMIORegWrite(Reg, Value) (*(volatile CARD32 *) (MMIOBase + (Reg))) = (Value)
+#define CSMMIORegRead(Reg) MMIO_IN32(MMIOBase, (Reg))
+#define CSMMIORegWrite(Reg, Value) MMIO_OUT32(MMIOBase, (Reg), (Value))
static void
CSMMIORBBMStuff(struct RhdCS *CS)
commit c9d1af91acc579d7930ecf221090ff558cbc2f99
Author: Yang Zhao <yang@yangman.ca>
Date: Fri Mar 27 19:46:11 2009 -0700
Use X MMIO macros instead of own register read/write functions
The old functions were not portable.
Signed-off-by: Yang Zhao <yang@yangman.ca>
diff --git a/src/r5xx_accel.c b/src/r5xx_accel.c
index 5264250..d7b94e0 100644
--- a/src/r5xx_accel.c
+++ b/src/r5xx_accel.c
@@ -121,9 +121,10 @@ R5xxFIFOWait(RHDPtr rhdPtr, CARD32 required)
static Bool
R5xx2DFlush(int scrnIndex)
{
+ ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
int i;
- _RHDRegMask(scrnIndex, R5XX_DSTCACHE_CTLSTAT,
+ RHDRegMask(pScrn, R5XX_DSTCACHE_CTLSTAT,
/* Radeon code:
R5XX_RB2D_DC_FLUSH_ALL, R5XX_RB2D_DC_FLUSH_ALL */
R5XX_DSTCACHE_FLUSH_ALL, R5XX_DSTCACHE_FLUSH_ALL);
@@ -131,11 +132,11 @@ R5xx2DFlush(int scrnIndex)
for (i = 0; i < R5XX_LOOP_COUNT; i++)
/* Radeon code:
& R5XX_RB2D_DC_BUSY */
- if (!(_RHDRegRead(scrnIndex, R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY))
+ if (!(RHDRegRead(pScrn, R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY))
return TRUE;
xf86DrvMsg(scrnIndex, X_ERROR, "%s: Timeout 0x%08x.\n", __func__,
- (unsigned int)_RHDRegRead(scrnIndex, R5XX_DSTCACHE_CTLSTAT));
+ (unsigned int) RHDRegRead(pScrn, R5XX_DSTCACHE_CTLSTAT));
return FALSE;
}
diff --git a/src/rhd.h b/src/rhd.h
index 818b40f..b4edf37 100644
--- a/src/rhd.h
+++ b/src/rhd.h
@@ -30,6 +30,8 @@
# error "config.h missing!"
# endif
+#include <compiler.h>
+
#define RHD_MAJOR_VERSION (PACKAGE_VERSION_MAJOR)
#define RHD_MINOR_VERSION (PACKAGE_VERSION_MINOR)
#define RHD_PATCHLEVEL (PACKAGE_VERSION_PATCHLEVEL)
@@ -376,12 +378,17 @@ extern Bool RHDScalePolicy(struct rhdMonitor *Monitor, struct rhdConnector *Conn
extern void RHDPrepareMode(RHDPtr rhdPtr);
extern Bool RHDUseAtom(RHDPtr rhdPtr, enum RHD_CHIPSETS *BlackList, enum atomSubSystem subsys);
-extern CARD32 _RHDRegRead(int scrnIndex, CARD16 offset);
-#define RHDRegRead(ptr, offset) _RHDRegRead((ptr)->scrnIndex, (offset))
-extern void _RHDRegWrite(int scrnIndex, CARD16 offset, CARD32 value);
-#define RHDRegWrite(ptr, offset, value) _RHDRegWrite((ptr)->scrnIndex, (offset), (value))
-extern void _RHDRegMask(int scrnIndex, CARD16 offset, CARD32 value, CARD32 mask);
-#define RHDRegMask(ptr, offset, value, mask) _RHDRegMask((ptr)->scrnIndex, (offset), (value), (mask))
+#define RHDRegRead(ptr, offset) MMIO_IN32(RHDPTRI(ptr)->MMIOBase, offset)
+#define RHDRegWrite(ptr, offset, value) MMIO_OUT32(RHDPTRI(ptr)->MMIOBase, offset, value)
+#define RHDRegMask(ptr, offset, value, mask) \
+do { \
+ CARD32 tmp; \
+ tmp = RHDRegRead(ptr, offset); \
+ tmp &= ~mask; \
+ tmp |= (value & mask); \
+ RHDRegWrite(ptr, offset, tmp); \
+} while(0)
+
extern CARD32 _RHDReadMC(int scrnIndex, CARD32 addr);
#define RHDReadMC(ptr,addr) _RHDReadMC((ptr)->scrnIndex,(addr))
extern void _RHDWriteMC(int scrnIndex, CARD32 addr, CARD32 data);
diff --git a/src/rhd_driver.c b/src/rhd_driver.c
index d32c11f..f7edb4a 100644
--- a/src/rhd_driver.c
+++ b/src/rhd_driver.c
@@ -2472,38 +2472,6 @@ rhdRestore(RHDPtr rhdPtr)
#endif
}
-/*
- *
- */
-CARD32
-_RHDRegRead(int scrnIndex, CARD16 offset)
-{
- return *(volatile CARD32 *)((CARD8 *) RHDPTR(xf86Screens[scrnIndex])->MMIOBase + offset);
-}
-
-/*
- *
- */
-void
-_RHDRegWrite(int scrnIndex, CARD16 offset, CARD32 value)
-{
- *(volatile CARD32 *)((CARD8 *) RHDPTR(xf86Screens[scrnIndex])->MMIOBase + offset) = value;
-}
-
-/*
- * This one might seem clueless, but it is an actual lifesaver.
- */
-void
-_RHDRegMask(int scrnIndex, CARD16 offset, CARD32 value, CARD32 mask)
-{
- CARD32 tmp;
-
- tmp = _RHDRegRead(scrnIndex, offset);
- tmp &= ~mask;
- tmp |= (value & mask);
- _RHDRegWrite(scrnIndex, offset, tmp);
-}
-
#ifdef RHD_DEBUG
/*
*
@@ -2511,7 +2479,7 @@ _RHDRegMask(int scrnIndex, CARD16 offset, CARD32 value, CARD32 mask)
CARD32
_RHDRegReadD(int scrnIndex, CARD16 offset)
{
- CARD32 tmp = *(volatile CARD32 *)((CARD8 *) RHDPTR(xf86Screens[scrnIndex])->MMIOBase + offset);
+ CARD32 tmp = MMIO_IN32(RHDPTR(xf86Screens[scrnIndex])->MMIOBase, offset);
xf86DrvMsg(scrnIndex, X_INFO, "RHDRegRead(0x%4.4x) = 0x%4.4x\n",offset,tmp);
return tmp;
}
@@ -2523,7 +2491,7 @@ void
_RHDRegWriteD(int scrnIndex, CARD16 offset, CARD32 value)
{
xf86DrvMsg(scrnIndex, X_INFO, "RHDRegWrite(0x%4.4x,0x%4.4x)\n",offset,tmp);
- *(volatile CARD32 *)((CARD8 *) RHDPTR(xf86Screens[scrnIndex])->MMIOBase + offset) = value;
+ MMIO_OUT32(RHDPTR(xf86Screens[scrnIndex])->MMIOBase, offset, value);
}
/*
@@ -2549,11 +2517,11 @@ _RHDReadMC(int scrnIndex, CARD32 addr)
CARD32 ret;
if (rhdPtr->ChipSet < RHD_RS600) {
- _RHDRegWrite(scrnIndex, MC_IND_INDEX, addr);
- ret = _RHDRegRead(scrnIndex, MC_IND_DATA);
+ RHDRegWrite(rhdPtr, MC_IND_INDEX, addr);
+ ret = RHDRegRead(rhdPtr, MC_IND_DATA);
} else if (rhdPtr->ChipSet == RHD_RS600) {
- _RHDRegWrite(scrnIndex, RS60_MC_NB_MC_INDEX, addr);
- ret = _RHDRegRead(scrnIndex, RS60_MC_NB_MC_DATA);
+ RHDRegWrite(rhdPtr, RS60_MC_NB_MC_INDEX, addr);
+ ret = RHDRegRead(rhdPtr, RS60_MC_NB_MC_DATA);
} else if (rhdPtr->ChipSet == RHD_RS690 || rhdPtr->ChipSet == RHD_RS740) {
#ifdef XSERVER_LIBPCIACCESS
CARD32 data = addr & ~RS69_MC_IND_WR_EN;
@@ -2591,11 +2559,11 @@ _RHDWriteMC(int scrnIndex, CARD32 addr, CARD32 data)
#endif
if (rhdPtr->ChipSet < RHD_RS600) {
- _RHDRegWrite(scrnIndex, MC_IND_INDEX, addr | MC_IND_WR_EN);
- _RHDRegWrite(scrnIndex, MC_IND_DATA, data);
+ RHDRegWrite(rhdPtr, MC_IND_INDEX, addr | MC_IND_WR_EN);
+ RHDRegWrite(rhdPtr, MC_IND_DATA, data);
} else if (rhdPtr->ChipSet == RHD_RS600) {
- _RHDRegWrite(scrnIndex, RS60_MC_NB_MC_INDEX, addr | RS60_NB_MC_IND_WR_EN);
- _RHDRegWrite(scrnIndex, RS60_MC_NB_MC_DATA, data);
+ RHDRegWrite(rhdPtr, RS60_MC_NB_MC_INDEX, addr | RS60_NB_MC_IND_WR_EN);
+ RHDRegWrite(rhdPtr, RS60_MC_NB_MC_DATA, data);
} else if (rhdPtr->ChipSet == RHD_RS690 || rhdPtr->ChipSet == RHD_RS740) {
#ifdef XSERVER_LIBPCIACCESS
CARD32 tmp = addr | RS69_MC_IND_WR_EN;
@@ -2622,15 +2590,17 @@ _RHDWriteMC(int scrnIndex, CARD32 addr, CARD32 data)
CARD32
_RHDReadPLL(int scrnIndex, CARD16 offset)
{
- _RHDRegWrite(scrnIndex, CLOCK_CNTL_INDEX, (offset & PLL_ADDR));
- return _RHDRegRead(scrnIndex, CLOCK_CNTL_DATA);
+ RHDPtr rhdPtr = RHDPTR(xf86Screens[scrnIndex]);
+ RHDRegWrite(rhdPtr, CLOCK_CNTL_INDEX, (offset & PLL_ADDR));
+ return RHDRegRead(rhdPtr, CLOCK_CNTL_DATA);
}
void
_RHDWritePLL(int scrnIndex, CARD16 offset, CARD32 data)
{
- _RHDRegWrite(scrnIndex, CLOCK_CNTL_INDEX, (offset & PLL_ADDR) | PLL_WR_EN);
- _RHDRegWrite(scrnIndex, CLOCK_CNTL_DATA, data);
+ RHDPtr rhdPtr = RHDPTR(xf86Screens[scrnIndex]);
+ RHDRegWrite(rhdPtr, CLOCK_CNTL_INDEX, (offset & PLL_ADDR) | PLL_WR_EN);
+ RHDRegWrite(rhdPtr, CLOCK_CNTL_DATA, data);
}
#ifdef ATOM_BIOS
commit f65014d8dd50eb0d72a1d9da5371db0840c16d7e
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Thu Apr 2 12:11:03 2009 -0400
Add RV790 (HD 4890) Support
diff --git a/src/rhd_id.c b/src/rhd_id.c
index 3c792ed..4a162c3 100644
--- a/src/rhd_id.c
+++ b/src/rhd_id.c
@@ -237,6 +237,8 @@ const PCI_ID_LIST = {
RHD_DEVICE_MATCH( 0x9456, RHD_RV770 ), /* Denali ATI FirePro Graphics Accelerator */
RHD_DEVICE_MATCH( 0x945A, RHD_M98 ), /* M98 */
RHD_DEVICE_MATCH( 0x945B, RHD_M98 ), /* M98 */
+ RHD_DEVICE_MATCH( 0x9460, RHD_RV770 ), /* RV790 */
+ RHD_DEVICE_MATCH( 0x9462, RHD_RV770 ), /* RV790 */
RHD_DEVICE_MATCH( 0x946A, RHD_M98 ), /* M98 */
RHD_DEVICE_MATCH( 0x946B, RHD_M98 ), /* M98 */
RHD_DEVICE_MATCH( 0x947A, RHD_M98 ), /* M98 */
commit 79efc6093f26daea654d3f748ebe3d4aa1229fe4
Author: Egbert Eich <eich@freedesktop.org>
Date: Wed Apr 1 09:38:41 2009 +0200
AtomBIOS: Fixed wrong logic: switch -> if.
diff --git a/src/rhd_atombios.c b/src/rhd_atombios.c
index 690e7a5..a285e48 100644
--- a/src/rhd_atombios.c
+++ b/src/rhd_atombios.c
@@ -1550,7 +1550,7 @@ rhdAtomEncoderControl(atomBiosHandlePtr handle, enum atomEncoder EncoderId,
lvds->ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_EN;
break;
}
- switch (Config->u.lvds2.SpatialDither)
+ if (Config->u.lvds2.SpatialDither)
lvds->ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_EN;
}
commit ecd616670e73d57397cc3e01017c84b9076c9f4f
Author: Yang Zhao <yang@yangman.ca>
Date: Sat Mar 21 15:21:50 2009 -0700
rhd_dump: fix error introduced by LUT dump addition
6e71f01f225a0cb13d10c7f7960db9d20c89a7db introduced a bug in rhd_dump
where register address is scanned as %d instead of %x.
Thanks to Rafal for pointing out the regression.
diff --git a/utils/conntest/rhd_dump.c b/utils/conntest/rhd_dump.c
index 4f17212..7a39026 100644
--- a/utils/conntest/rhd_dump.c
+++ b/utils/conntest/rhd_dump.c
@@ -433,7 +433,7 @@ main(int argc, char *argv[])
action = WRITE;
if (++i < argc)
- ret = sscanf(argv[i++], "%d", &addr);
+ ret = sscanf(argv[i++], "%x", &addr);
else {
i--;
ret = 0;
commit 7e4948a3ad80ae0885df89ac7320457cb90f0b55
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Thu Mar 26 14:22:35 2009 -0400
R6xx/R7xx EXA: rework composite pixel shader
- move to vram storage
- move swizzle logic to tex setup
diff --git a/src/r600_exa.c b/src/r600_exa.c
index d9c4ca5..86da7af 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -1104,6 +1104,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
unsigned int i;
tex_resource_t tex_res;
tex_sampler_t tex_samp;
+ int pix_r, pix_g, pix_b, pix_a;
CLEAR (tex_res);
CLEAR (tex_samp);
@@ -1148,46 +1149,102 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
switch (pPict->format) {
case PICT_a1r5g5b5:
case PICT_a8r8g8b8:
- tex_res.dst_sel_x = SQ_SEL_Z; /* R */
- tex_res.dst_sel_y = SQ_SEL_Y; /* G */
- tex_res.dst_sel_z = SQ_SEL_X; /* B */
- tex_res.dst_sel_w = SQ_SEL_W; /* A */
+ pix_r = SQ_SEL_Z; /* R */
+ pix_g = SQ_SEL_Y; /* G */
+ pix_b = SQ_SEL_X; /* B */
+ pix_a = SQ_SEL_W; /* A */
break;
case PICT_a8b8g8r8:
- tex_res.dst_sel_x = SQ_SEL_X; /* R */
- tex_res.dst_sel_y = SQ_SEL_Y; /* G */
- tex_res.dst_sel_z = SQ_SEL_Z; /* B */
- tex_res.dst_sel_w = SQ_SEL_W; /* A */
+ pix_r = SQ_SEL_X; /* R */
+ pix_g = SQ_SEL_Y; /* G */
+ pix_b = SQ_SEL_Z; /* B */
+ pix_a = SQ_SEL_W; /* A */
break;
case PICT_x8b8g8r8:
- tex_res.dst_sel_x = SQ_SEL_X; /* R */
- tex_res.dst_sel_y = SQ_SEL_Y; /* G */
- tex_res.dst_sel_z = SQ_SEL_Z; /* B */
- tex_res.dst_sel_w = SQ_SEL_1; /* A */
+ pix_r = SQ_SEL_X; /* R */
+ pix_g = SQ_SEL_Y; /* G */
+ pix_b = SQ_SEL_Z; /* B */
+ pix_a = SQ_SEL_1; /* A */
break;
case PICT_x1r5g5b5:
case PICT_x8r8g8b8:
- tex_res.dst_sel_x = SQ_SEL_Z; /* R */
- tex_res.dst_sel_y = SQ_SEL_Y; /* G */
- tex_res.dst_sel_z = SQ_SEL_X; /* B */
- tex_res.dst_sel_w = SQ_SEL_1; /* A */
- break;
case PICT_r5g6b5:
- tex_res.dst_sel_x = SQ_SEL_Z; /* R */
- tex_res.dst_sel_y = SQ_SEL_Y; /* G */
- tex_res.dst_sel_z = SQ_SEL_X; /* B */
- tex_res.dst_sel_w = SQ_SEL_1; /* A */
+ pix_r = SQ_SEL_Z; /* R */
+ pix_g = SQ_SEL_Y; /* G */
+ pix_b = SQ_SEL_X; /* B */
+ pix_a = SQ_SEL_1; /* A */
break;
case PICT_a8:
- tex_res.dst_sel_x = SQ_SEL_0; /* R */
- tex_res.dst_sel_y = SQ_SEL_0; /* G */
- tex_res.dst_sel_z = SQ_SEL_0; /* B */
- tex_res.dst_sel_w = SQ_SEL_X; /* A */
+ pix_r = SQ_SEL_0; /* R */
+ pix_g = SQ_SEL_0; /* G */
+ pix_b = SQ_SEL_0; /* B */
+ pix_a = SQ_SEL_X; /* A */
break;
default:
RADEON_FALLBACK(("Bad format 0x%x\n", pPict->format));
}
+ if (unit == 0) {
+ if (!accel_state->has_mask) {
+ if (PICT_FORMAT_RGB(pPict->format) == 0) {
+ pix_r = SQ_SEL_0;
+ pix_g = SQ_SEL_0;
+ pix_b = SQ_SEL_0;
+ }
+
+ if (PICT_FORMAT_A(pPict->format) == 0)
+ pix_a = SQ_SEL_1;
+ } else {
+ if (accel_state->component_alpha) {
+ if (accel_state->src_alpha) {
+ if (PICT_FORMAT_A(pPict->format) == 0) {
+ pix_r = SQ_SEL_1;
+ pix_g = SQ_SEL_1;
+ pix_b = SQ_SEL_1;
+ pix_a = SQ_SEL_1;
+ } else {
+ pix_r = pix_a;
+ pix_g = pix_a;
+ pix_b = pix_a;
+ }
+ } else {
+ if (PICT_FORMAT_A(pPict->format) == 0)
+ pix_a = SQ_SEL_1;
+ }
+ } else {
+ if (PICT_FORMAT_RGB(pPict->format) == 0) {
+ pix_r = SQ_SEL_0;
+ pix_g = SQ_SEL_0;
+ pix_b = SQ_SEL_0;
+ }
+
+ if (PICT_FORMAT_A(pPict->format) == 0)
+ pix_a = SQ_SEL_1;
+ }
+ }
+ } else {
+ if (accel_state->component_alpha) {
+ if (PICT_FORMAT_A(pPict->format) == 0)
+ pix_a = SQ_SEL_1;
+ } else {
+ if (PICT_FORMAT_A(pPict->format) == 0) {
+ pix_r = SQ_SEL_1;
+ pix_g = SQ_SEL_1;
+ pix_b = SQ_SEL_1;
+ pix_a = SQ_SEL_1;
+ } else {
+ pix_r = pix_a;
+ pix_g = pix_a;
+ pix_b = pix_a;
+ }
+ }
+ }
+
+ tex_res.dst_sel_x = pix_r; /* R */
+ tex_res.dst_sel_y = pix_g; /* G */
+ tex_res.dst_sel_z = pix_b; /* B */
+ tex_res.dst_sel_w = pix_a; /* A */
+
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
@@ -1333,14 +1390,26 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
uint32_t blendcntl, dst_format;
cb_config_t cb_conf;
shader_config_t vs_conf, ps_conf;
- uint32_t ps[24];
/* return FALSE; */
- if (pMask)
+ if (pMask) {
accel_state->has_mask = TRUE;
- else
+ if (pMaskPicture->componentAlpha) {
+ accel_state->component_alpha = TRUE;
+ if (R600BlendOp[op].src_alpha)
+ accel_state->src_alpha = TRUE;
+ else
+ accel_state->src_alpha = FALSE;
+ } else {
+ accel_state->component_alpha = FALSE;
+ accel_state->src_alpha = FALSE;
+ }
+ } else {
accel_state->has_mask = FALSE;
+ accel_state->component_alpha = FALSE;
+ accel_state->src_alpha = FALSE;
+ }
accel_state->dst_mc_addr = exaGetPixmapOffset(pDst) + rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart;
accel_state->dst_pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
@@ -1355,142 +1424,6 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
if (!R600GetDestFormat(pDstPicture, &dst_format))
return FALSE;
- if (pMask) {
- int src_a, src_r, src_g, src_b;
- int mask_a, mask_r, mask_g, mask_b;
-
- /* setup pixel shader */
- if (PICT_FORMAT_RGB(pSrcPicture->format) == 0) {
- /* src_color = R300_ALU_RGB_0_0; */
- src_r = SQ_SEL_0;
- src_g = SQ_SEL_0;
- src_b = SQ_SEL_0;
- } else {
- /* src_color = R300_ALU_RGB_SRC0_RGB; */
- src_r = SQ_SEL_X;
- src_g = SQ_SEL_Y;
- src_b = SQ_SEL_Z;
- }
-
- if (PICT_FORMAT_A(pSrcPicture->format) == 0) {
- /* src_alpha = R300_ALU_ALPHA_1_0; */
- src_a = SQ_SEL_1;
- } else {
- /* src_alpha = R300_ALU_ALPHA_SRC0_A; */
- src_a = SQ_SEL_W;
- }
-
- if (pMaskPicture->componentAlpha) {
- if (R600BlendOp[op].src_alpha) {
- if (PICT_FORMAT_A(pSrcPicture->format) == 0) {
- /* src_color = R300_ALU_RGB_1_0; */
- /* src_alpha = R300_ALU_ALPHA_1_0; */
- src_r = SQ_SEL_1;
- src_g = SQ_SEL_1;
- src_b = SQ_SEL_1;
- src_a = SQ_SEL_1;
- } else {
- /* src_color = R300_ALU_RGB_SRC0_AAA; */
- /* src_alpha = R300_ALU_ALPHA_SRC0_A; */
- src_r = SQ_SEL_W;
- src_g = SQ_SEL_W;
- src_b = SQ_SEL_W;
- src_a = SQ_SEL_W;
- }
-
- /* mask_color = R300_ALU_RGB_SRC1_RGB; */
- mask_r = SQ_SEL_X;
- mask_g = SQ_SEL_Y;
- mask_b = SQ_SEL_Z;
-
- if (PICT_FORMAT_A(pMaskPicture->format) == 0) {
- /* mask_alpha = R300_ALU_ALPHA_1_0; */
- mask_a = SQ_SEL_1;
- } else {
- /* mask_alpha = R300_ALU_ALPHA_SRC1_A; */
- mask_a = SQ_SEL_W;
- }
- } else {
- /* src_color = R300_ALU_RGB_SRC0_RGB; */
- src_r = SQ_SEL_X;
- src_g = SQ_SEL_Y;
- src_b = SQ_SEL_Z;
-
- if (PICT_FORMAT_A(pSrcPicture->format) == 0) {
- /* src_alpha = R300_ALU_ALPHA_1_0; */
- src_a = SQ_SEL_1;
- } else {
- /* src_alpha = R300_ALU_ALPHA_SRC0_A; */
- src_a = SQ_SEL_W;
- }
-
- /* mask_color = R300_ALU_RGB_SRC1_RGB; */
- mask_r = SQ_SEL_X;
- mask_g = SQ_SEL_Y;
- mask_b = SQ_SEL_Z;
-
- if (PICT_FORMAT_A(pMaskPicture->format) == 0) {
- /* mask_alpha = R300_ALU_ALPHA_1_0; */
- mask_a = SQ_SEL_1;
- } else {
- /* mask_alpha = R300_ALU_ALPHA_SRC1_A; */
- mask_a = SQ_SEL_W;
- }
- }
- } else {
- if (PICT_FORMAT_A(pMaskPicture->format) == 0) {
- /* mask_color = R300_ALU_RGB_1_0; */
- mask_r = SQ_SEL_1;
- mask_g = SQ_SEL_1;
- mask_b = SQ_SEL_1;
- } else {
- /* mask_color = R300_ALU_RGB_SRC1_AAA; */
- mask_r = SQ_SEL_W;
- mask_g = SQ_SEL_W;
- mask_b = SQ_SEL_W;
- }
- if (PICT_FORMAT_A(pMaskPicture->format) == 0) {
- /* mask_alpha = R300_ALU_ALPHA_1_0; */
- mask_a = SQ_SEL_1;
- } else {
- /* mask_alpha = R300_ALU_ALPHA_SRC1_A; */
- mask_a = SQ_SEL_W;
- }
- }
-
- R600_comp_mask_ps(rhdPtr->ChipSet, ps,
- src_a, src_r, src_g, src_b,
- mask_a, mask_r, mask_g, mask_b
- );
-
- } else {
- int src_a, src_r, src_g, src_b;
- /* setup pixel shader */
- if (PICT_FORMAT_RGB(pSrcPicture->format) == 0) {
- /* src_color = R300_ALU_RGB_0_0; */
- src_r = SQ_SEL_0;
- src_g = SQ_SEL_0;
- src_b = SQ_SEL_0;
- } else {
- /* src_color = R300_ALU_RGB_SRC0_RGB; */
- src_r = SQ_SEL_X;
- src_g = SQ_SEL_Y;
- src_b = SQ_SEL_Z;
- }
-
- if (PICT_FORMAT_A(pSrcPicture->format) == 0) {
- /* src_alpha = R300_ALU_ALPHA_1_0; */
- src_a = SQ_SEL_1;
- } else {
- /* src_alpha = R300_ALU_ALPHA_SRC0_A; */
- src_a = SQ_SEL_W;
- }
-
- R600_comp_ps(rhdPtr->ChipSet, ps,
- src_a, src_r, src_g, src_b
- );
- }
-
CLEAR (cb_conf);
CLEAR (vs_conf);
CLEAR (ps_conf);
@@ -1521,19 +1454,19 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
} else
accel_state->is_transform[1] = FALSE;
- /* VS bool constant */
- if (pMask)
+ if (pMask) {
set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (1 << 0));
- else
+ accel_state->ps_mc_addr = rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart + accel_state->shaders->offset +
+ accel_state->comp_mask_ps_offset;
+ } else {
set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (0 << 0));
+ accel_state->ps_mc_addr = rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart + accel_state->shaders->offset +
+ accel_state->comp_ps_offset;
+ }
accel_state->vs_mc_addr = rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart + accel_state->shaders->offset +
accel_state->comp_vs_offset;
- memcpy ((char *)accel_state->ib->address + (accel_state->ib->total / 2) - 256, ps, sizeof(ps));
- accel_state->ps_mc_addr = RHDDRIGetIntGARTLocation(pScrn) +
- (accel_state->ib->idx * accel_state->ib->total) + (accel_state->ib->total / 2) - 256;
-
accel_state->vs_size = 512;
accel_state->ps_size = 512;
@@ -2085,11 +2018,11 @@ R600LoadShaders(ScrnInfoPtr pScrn)
/* comp ps --------------------------------------- */
accel_state->comp_ps_offset = 2560;
- /* not yet */
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