xserver-xorg-video-ati: Changes to 'debian-experimental'
ChangeLog | 375 ++++++++++++
debian/changelog | 9
src/ati.c | 2
src/ati.h | 2
src/ati_pciids_gen.h | 6
src/atimodule.c | 2
src/atombios_crtc.c | 13
src/atombios_output.c | 101 ++-
src/legacy_output.c | 2
src/pcidb/ati_pciids.csv | 8
src/radeon.h | 380 +++++++------
src/radeon_atombios.c | 725 +-----------------------
src/radeon_atomwrapper.c | 2
src/radeon_chipinfo_gen.h | 8
src/radeon_chipset_gen.h | 6
src/radeon_crtc.c | 11
src/radeon_cursor.c | 8
src/radeon_driver.c | 80 --
src/radeon_exa.c | 9
src/radeon_exa_funcs.c | 4
src/radeon_exa_render.c | 1103 +++++++++++++++++++++++++++-----------
src/radeon_output.c | 142 +++-
src/radeon_pci_chipset_gen.h | 6
src/radeon_pci_device_match_gen.h | 6
src/radeon_probe.h | 6
src/radeon_reg.h | 187 +++++-
src/radeon_render.c | 9
src/radeon_textured_video.c | 22
src/radeon_textured_videofuncs.c | 100 ++-
src/theatre_detect.c | 1
30 files changed, 1961 insertions(+), 1374 deletions(-)
New commits:
commit 1e44fc13b9fce0e846fe5ba61fb7851049acc449
Author: Brice Goglin <bgoglin@debian.org>
Date: Thu Mar 20 09:10:29 2008 +0100
Prepare changelog for upload
diff --git a/debian/changelog b/debian/changelog
index 222b905..9590b56 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,11 +1,11 @@
-xserver-xorg-video-ati (1:6.8.1~git20080320.5e3b2128-1) UNRELEASED; urgency=low
+xserver-xorg-video-ati (1:6.8.1~git20080320.5e3b2128-1) experimental; urgency=low
* New upstream snapshot, up to commit 5e3b2128.
+ Driver-side fix of two colour cursors to ARGB conversion on
big endian platforms, needs a recent xserver-xorg-core to be
be complete, closes: #446123.
- -- Brice Goglin <bgoglin@debian.org> Thu, 20 Mar 2008 09:04:23 +0100
+ -- Brice Goglin <bgoglin@debian.org> Thu, 20 Mar 2008 09:10:18 +0100
xserver-xorg-video-ati (1:6.8.1~git20080310.38606b08-1) experimental; urgency=low
commit 7a7d44e34827f99bf99617ecaa689da99b8fb895
Author: Brice Goglin <bgoglin@debian.org>
Date: Thu Mar 20 09:08:39 2008 +0100
New upstream snapshot
diff --git a/ChangeLog b/ChangeLog
index 5a6d3b1..82ac668 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,378 @@
+commit 5e3b21284482df9974c9a58f248f0100def2bb0c
+Author: Alex Deucher <alex@samba.(none)>
+Date: Wed Mar 19 19:15:05 2008 -0400
+
+ Disable the setting of HARDWARE_CURSOR_BIT_ORDER_MSBFIRST
+
+ See bug 11796
+
+commit 17cd42ed31814ba329a6a68edd0d75390a7da40e
+Author: Matt Turner <mattst88@gmail.com>
+Date: Wed Mar 19 18:17:10 2008 -0400
+
+ Enable BSR in Log2 functions
+
+ This patch edits RADEONLog2 and ATILog2 to use the x86 BSR instruction instead
+ of looping through bits. It should provide a somewhat of a speed increase in
+ this function on x86 and AMD64 architectures.
+
+ Note: the BSR instruction was added with the 80386 CPU and is therefore not
+ compatible with earlier CPUs, though I highly doubt it's even possible to use a
+ 286 in conjunction with a Radeon.
+
+ The inline assembly also works with Intel's compiler (icc).
+
+commit c83827b4d2b6f03c54429e757a756eb99ff8be6b
+Author: Paulo Cesar Pereira de Andrade <pcpa@mandriva.com.br>
+Date: Wed Mar 19 17:58:34 2008 -0400
+
+ [PATCH] Compile warning fixes.
+
+ Minor changes to avoid declarations mixed with code.
+ Ansified functions with empty prototype to specify they don't
+ receive arguments.
+ Added some prototypes to radeon.h, and major reorder on radeon.h
+ adding prototypes in alphabetical order and specifying to file that
+ defines it.
+
+commit bed9754ad21d6c0a7f61067b04ba31c430a7cecb
+Merge: 55e446b... f71ac0e...
+Author: Alex Deucher <alex@samba.(none)>
+Date: Wed Mar 19 16:06:41 2008 -0400
+
+ Merge branch 'master' of ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati into r3xx-render
+
+commit 55e446b5bc091e6c7b3c2e9ae20b45130555c246
+Author: Alex Deucher <alex@samba.(none)>
+Date: Wed Mar 19 13:15:32 2008 -0400
+
+ R3xx/R5xx: Make sure to clamp the output of the FS
+
+commit b6aa4279cbe68cc8e4523795e9714fb798b62d98
+Author: Alex Deucher <alex@samba.(none)>
+Date: Wed Mar 19 12:45:01 2008 -0400
+
+ R5xx: bump textured video limits to 4096
+
+commit 4a445a3e8c4c5ecd9d4ef8daa26906c3ceaa94a1
+Author: Alex Deucher <alex@samba.(none)>
+Date: Wed Mar 19 12:31:51 2008 -0400
+
+ RADEON: add new macros to distinguish between R3xx and R5xx 3D
+
+commit 85d0c9e8d22ccc72bec87b3fd44da5d7609293e0
+Author: Alex Deucher <alex@samba.(none)>
+Date: Wed Mar 19 12:07:33 2008 -0400
+
+ RADEON: fixed textured video with XAA and tiling
+
+commit f5951db7b3522e0fe6af7f46a170c9c9a60a9bff
+Author: Alex Deucher <alex@samba.(none)>
+Date: Wed Mar 19 12:01:50 2008 -0400
+
+ RV515: fix textured video and EXA Composite
+
+ There seems to be an issue with the PVS setup on RV515, but
+ bypassing it seems to work fine.
+
+commit 13573879fe56368ad06234712b677c23fabc56c6
+Author: Dave Airlie <airlied@redhat.com>
+Date: Wed Mar 19 15:06:47 2008 +1000
+
+ r500: make it work from startup.
+
+ I'm not sure why this worked or what is going wrong here, really the
+ VAP internal architecture escapes me :)
+
+commit d331dd64d644a18ec99a2136cd0943b5edca1f03
+Author: Alex Deucher <alex@samba.(none)>
+Date: Tue Mar 18 19:44:26 2008 -0400
+
+ R3xx/R5xx: remove extra return after last commit
+
+commit bc34df7a9c35cdd38c49d5c22471f3f487a33d6e
+Author: Alex Deucher <alex@samba.(none)>
+Date: Tue Mar 18 19:39:47 2008 -0400
+
+ R3xx/R5xx: switch an ErrorF() to RADEONFALLBACK()
+
+commit 6f03f8fe0ecf4181dcf125049cf63bece0451fb2
+Author: Alex Deucher <alex@samba.(none)>
+Date: Tue Mar 18 19:36:05 2008 -0400
+
+ R3xx: we only use 2 temps, not 3
+
+commit 8bb71ab4a3eb4fb6ef7f709e87c8df387cb70ee3
+Author: Tilman Sauerbeck <tilman@code-monkey.de>
+Date: Tue Mar 18 14:36:08 2008 -0400
+
+ R3xx/R5xx: fix up a8-src-something_with_colors
+
+commit c362591d9b496df30668543158e4de44de742dc3
+Author: Alex Deucher <alex@samba.(none)>
+Date: Tue Mar 18 11:15:17 2008 -0400
+
+ R3xx/R5xx: remove some cruft
+
+commit 89fe6d2c7d7471e6088558130f6e49f46c31dd47
+Author: Dave Airlie <airlied@linux.ie>
+Date: Tue Mar 18 09:43:43 2008 -0400
+
+ R5xx: fix typ in r5xx render accel
+
+ This gets render working on r5xx
+
+commit 79b40ebcd8dedfc83e484c1024beeeaccc6124f3
+Author: Alex Deucher <alex@samba.(none)>
+Date: Tue Mar 18 02:46:49 2008 -0400
+
+ R5xx: first pass at render support (untested)
+
+commit 71292c8f193230255d1d980c2e996bb01d04fab6
+Author: Alex Deucher <alex@samba.(none)>
+Date: Tue Mar 18 00:45:37 2008 -0400
+
+ R5xx: bump tex/dst limits to 4096
+
+commit 30b52f8aa6a471455284f59b5b27252743892b13
+Author: Alex Deucher <alex@samba.(none)>
+Date: Mon Mar 17 23:20:10 2008 -0400
+
+ R3xx/R5xx: whitespace cleanup and cruft removal
+
+commit 9c9f1b538ed710c3066775fba0a8e936b63087b1
+Author: Alex Deucher <alex@samba.(none)>
+Date: Mon Mar 17 23:01:37 2008 -0400
+
+ R3xx: get masks working and cleanup
+
+ RS offset was wrong for mask texture
+
+commit ef94febd74f8ee63081b61e42f093a5a2b8fbf1e
+Author: Alex Deucher <alex@samba.(none)>
+Date: Mon Mar 17 22:27:19 2008 -0400
+
+ R3xx: minor adjustments
+
+commit f71ac0e40b9d950bcb3bba42a75d41f45b6ed1bf
+Author: Alban Browaeys <prahal@yahoo.com>
+Date: Mon Mar 17 20:48:48 2008 -0400
+
+ RADEON: Revert to old behavior when resetting the memmap on VT switch
+
+ Not sure why this needs to be done twice. Should fix bug 14980
+ Probably needs more investigation.
+
+commit bedbbf196dc97ee5142e7dfae16fb6f317fca5a7
+Author: Alex Deucher <alex@samba.(none)>
+Date: Mon Mar 17 20:16:25 2008 -0400
+
+ R3xx: some progress
+
+commit af0e626c132de2dd9958fec657fcc85d4c0fe5e1
+Author: Alex Deucher <alex@samba.(none)>
+Date: Mon Mar 17 18:07:12 2008 -0400
+
+ R3xx: fix errant w
+
+commit 29ea5bfc0eb3194e2454fc3ee863df54f0300880
+Author: Alex Deucher <alex@cube.(none)>
+Date: Mon Mar 17 16:41:57 2008 -0400
+
+ RADEON: fix typo in RADEONAdjustMemMapRegisters()
+
+commit ab317e85c5ab1a249a510c34aeb3a908be1a66fc
+Author: Alex Deucher <alex@cube.(none)>
+Date: Mon Mar 17 15:28:09 2008 -0400
+
+ RADEON: make sure var is initialized properly in RADEONAdjustMemMapRegisters()
+
+commit 208d307227e15f37a6af5194398ed23266ff743a
+Author: Dave Airlie <airlied@linux.ie>
+Date: Sun Mar 16 19:39:23 2008 +1000
+
+ radeon: the 0x5974 appears to be a mobility chip...
+
+ After debugging with partymola on #radeon, adding this allowed his
+ Dell Vostro 1000 to work properly
+
+commit 9bc7c2ec4048e1677547c1d60c51ccb954f7589a
+Author: Alex Deucher <alex@samba.(none)>
+Date: Fri Mar 14 20:12:22 2008 -0400
+
+ R3xx: odds and ends...
+
+ still not working.
+ - swizzle US output for BGR formats
+ - no need to write to temps in ALU ops,
+ write to output only
+ - flush the PVS before updating
+
+commit 96bea7906c4706fcd57a9cd8f1ce3feab6ac676d
+Author: Alex Deucher <alex@samba.(none)>
+Date: Fri Mar 14 15:59:36 2008 -0400
+
+ R3xx: theoretical support for component alpha
+
+ masks are still broken so...
+
+commit cffe3dcc8991cd7c457a9c1a9f41055aa9ea3436
+Author: Alex Deucher <alex@samba.(none)>
+Date: Fri Mar 14 14:37:43 2008 -0400
+
+ R3xx: VS WIP
+
+commit b73f52a50dfd6ff8d92f04d6b510c39582c6ac67
+Author: Alex Deucher <alex@samba.(none)>
+Date: Fri Mar 14 14:20:49 2008 -0400
+
+ R3xx/R5xx: enable VS for mask texture
+
+commit 569a14ca9be1e18fe9921edc816ac3dc32d6cca7
+Author: Alex Deucher <alex@samba.(none)>
+Date: Fri Mar 14 13:32:12 2008 -0400
+
+ R3xx/R5xx: Fix magic numbers in vertex shaders
+
+commit 4878997529601d62e257aa1c9112bd460561de73
+Author: Alex Deucher <alex@samba.(none)>
+Date: Thu Mar 13 21:23:40 2008 -0400
+
+ R3xx: make sure to set the FS code size correctly
+
+commit 22f46b88ef05afb6a6b6d70007ac4980a446430e
+Author: Alex Deucher <alex@samba.(none)>
+Date: Thu Mar 13 20:25:33 2008 -0400
+
+ R3xx: attempt to setup the rasterizer properly for mask texture
+
+ Not working yet
+
+commit 081fc9e892fa3d2e07b7db65b2e2719646255463
+Author: Alex Deucher <alex@samba.(none)>
+Date: Thu Mar 13 18:38:26 2008 -0400
+
+ R3xx: more mask work
+
+commit 2bf0236c03538ace3ce6d0e68f0829fc47d1385b
+Author: Alex Deucher <alex@samba.(none)>
+Date: Thu Mar 13 18:32:00 2008 -0400
+
+ R3xx: enable composite for non-mask cases
+
+commit 74286ba41302107d2fc626fee2181f7c4bc18164
+Author: Alex Deucher <alex@samba.(none)>
+Date: Thu Mar 13 18:25:32 2008 -0400
+
+ R3xx: add basic mask support
+
+commit a2bbe10d866567911b68f222b4758624bfe9bf84
+Author: Alex Deucher <alex@samba.(none)>
+Date: Thu Mar 13 18:16:53 2008 -0400
+
+ R300: setup source selects and output swizzling
+
+commit b9974ecce7d1932595226004858b08a7a6b188dc
+Author: Alex Deucher <alex@samba.(none)>
+Date: Thu Mar 13 17:35:38 2008 -0400
+
+ R3xx: set the texture id and add some register info
+
+commit 0ef700b7da5e554a0d0d166f3fde85ff45c9eb1f
+Author: Alex Deucher <alex@samba.(none)>
+Date: Thu Mar 13 17:02:25 2008 -0400
+
+ R3xx/R5xx: enable blending
+
+commit b35c09a597c93a1d9f06ef0091c96822b0653f98
+Author: Dave Airlie <airlied@redhat.com>
+Date: Thu Mar 13 18:42:29 2008 +1000
+
+ xv: fixup XAA on r500 textured video
+
+ the XAA area should never end up tiled. This may break with nooffscreen pixmaps
+
+commit d4446461c3630caff166456c351ace34f57cc119
+Author: Matt Turner <mattst88@gmail.com>
+Date: Tue Mar 11 21:20:53 2008 -0400
+
+ Properly fix uninitialized variables warnings
+
+ According to commit 9fd13e6773371c82b9799a5bda7c96ffa5cafe8c to
+ xf86-video-intel by Kristian Høgsberg, there is a better way to fix the
+ possibly initialized variables warnings. This patch will use Kristian's fix.
+
+commit 20adfd7390d9b1f100e0c4a14f175377b8335c82
+Author: Alex Deucher <alex@cube.(none)>
+Date: Tue Mar 11 20:09:35 2008 -0400
+
+ RADEON: enable output attributes that require a modeset immediately
+
+ This should fix bug 14915
+
+commit 53ba7f5771b0b53fb0d3bc29d64bdd3813756d10
+Author: Alex Deucher <alex@cube.(none)>
+Date: Tue Mar 11 19:12:40 2008 -0400
+
+ RADEON: fix vblank interrupts after VT switch or suspend/resume
+
+commit e946c097f0438afbea6f3dd37ee39d67d415708c
+Author: Matt Turner <mattst88@gmail.com>
+Date: Tue Mar 11 19:07:58 2008 -0400
+
+ [PATCH] Fix a few warnings
+
+commit 8e160508520c0a24ca90aad182f296461ca0d9b6
+Author: Alex Deucher <alex@cube.(none)>
+Date: Tue Mar 11 18:11:13 2008 -0400
+
+ DCE3: add support for PCIEPHY (untested)
+
+commit fbded88a2925f9f049936dad0736721e7b84a6ee
+Author: Alex Deucher <alex@cube.(none)>
+Date: Tue Mar 11 14:10:31 2008 -0400
+
+ ATOM: remove some cruft
+
+commit 3263f6e4a410281d620c288a92bb4521f7b6fc06
+Author: Alex Deucher <alex@cube.(none)>
+Date: Tue Mar 11 14:05:48 2008 -0400
+
+ DCE3: enable DPMS on DIG ports
+
+commit eb90e235b58c94f3d4d75394725ab2fe246a42ff
+Author: Alex Deucher <alex@cube.(none)>
+Date: Tue Mar 11 13:53:54 2008 -0400
+
+ DCE3: adjust PLL for DCE3 chips
+
+ this fixes stability issues on digital outputs and certain modes.
+
+commit 552615ccc5360baafb8bb41698c1ca27816fd4b2
+Author: Alex Deucher <alex@cube.(none)>
+Date: Tue Mar 11 13:38:29 2008 -0400
+
+ ATOMBIOS: enable load detection by default on both DACs
+
+ Load detection is reliable with atom, so enable it by default
+ on both DACA and DACB, rather than just DACA.
+
+commit 78b10487cf222c96f8944ba25e2ea970506b3535
+Author: Alex Deucher <alex@cube.(none)>
+Date: Tue Mar 11 13:16:00 2008 -0400
+
+ DCE3: add output attribute to enable/disable coherent mode
+
+ Enabled by default. The TMDS transmitter can be programmed
+ slightly differently depending on the chips in the panel. If you
+ have problems with tmds on a particular panel, try disabling it.
+
+commit d20be31c46fbec623af4c3628a7c603ceacf500f
+Author: Alex Deucher <alex@botch2.(none)>
+Date: Mon Mar 10 21:05:43 2008 -0400
+
+ RV550: MC setup is like RV515 not RV530
+
commit 38606b08b68842fbcc81c233009c1117269f3be9
Author: Matthieu Herrb <matthieu@bluenote.herrb.net>
Date: Sat Mar 8 23:22:59 2008 +0100
diff --git a/debian/changelog b/debian/changelog
index 7c2dd2f..222b905 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,12 @@
+xserver-xorg-video-ati (1:6.8.1~git20080320.5e3b2128-1) UNRELEASED; urgency=low
+
+ * New upstream snapshot, up to commit 5e3b2128.
+ + Driver-side fix of two colour cursors to ARGB conversion on
+ big endian platforms, needs a recent xserver-xorg-core to be
+ be complete, closes: #446123.
+
+ -- Brice Goglin <bgoglin@debian.org> Thu, 20 Mar 2008 09:04:23 +0100
+
xserver-xorg-video-ati (1:6.8.1~git20080310.38606b08-1) experimental; urgency=low
* New upstream snapshap, up to commit 38606b08.
commit 5e3b21284482df9974c9a58f248f0100def2bb0c
Author: Alex Deucher <alex@samba.(none)>
Date: Wed Mar 19 19:15:05 2008 -0400
Disable the setting of HARDWARE_CURSOR_BIT_ORDER_MSBFIRST
See bug 11796
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index 0f7e668..de64dee 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -346,14 +346,6 @@ Bool RADEONCursorInit(ScreenPtr pScreen)
return xf86_cursors_init (pScreen, CURSOR_WIDTH, CURSOR_HEIGHT,
(HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* this is a lie --
- * HARDWARE_CURSOR_BIT_ORDER_MSBFIRST
- * actually inverts the bit order, so
- * this switches to LSBFIRST
- */
- HARDWARE_CURSOR_BIT_ORDER_MSBFIRST |
-#endif
HARDWARE_CURSOR_AND_SOURCE_WITH_MASK |
HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 |
HARDWARE_CURSOR_ARGB));
commit 17cd42ed31814ba329a6a68edd0d75390a7da40e
Author: Matt Turner <mattst88@gmail.com>
Date: Wed Mar 19 18:17:10 2008 -0400
Enable BSR in Log2 functions
This patch edits RADEONLog2 and ATILog2 to use the x86 BSR instruction instead
of looping through bits. It should provide a somewhat of a speed increase in
this function on x86 and AMD64 architectures.
Note: the BSR instruction was added with the 80386 CPU and is therefore not
compatible with earlier CPUs, though I highly doubt it's even possible to use a
286 in conjunction with a Radeon.
The inline assembly also works with Intel's compiler (icc).
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 4da4841..a6ededa 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -99,10 +99,17 @@ static __inline__ int
RADEONLog2(int val)
{
int bits;
-
+#if (defined __i386__ || defined __x86_64__) && (defined __GNUC__)
+ __asm volatile("bsrl %1, %0"
+ : "=r" (bits)
+ : "c" (val)
+ );
+ return bits;
+#else
for (bits = 0; val != 0; val >>= 1, ++bits)
;
return bits - 1;
+#endif
}
static __inline__ CARD32 F_TO_DW(float val)
diff --git a/src/radeon_render.c b/src/radeon_render.c
index a80d136..950753c 100644
--- a/src/radeon_render.c
+++ b/src/radeon_render.c
@@ -250,10 +250,17 @@ static __inline__ int
ATILog2(int val)
{
int bits;
-
+#if (defined __i386__ || defined __x86_64__) && (defined __GNUC__)
+ __asm volatile("bsrl %1, %0"
+ : "=r" (bits)
+ : "c" (val)
+ );
+ return bits;
+#else
for (bits = 0; val != 0; val >>= 1, ++bits)
;
return bits - 1;
+#endif
}
static void
commit c83827b4d2b6f03c54429e757a756eb99ff8be6b
Author: Paulo Cesar Pereira de Andrade <pcpa@mandriva.com.br>
Date: Wed Mar 19 17:58:34 2008 -0400
[PATCH] Compile warning fixes.
Minor changes to avoid declarations mixed with code.
Ansified functions with empty prototype to specify they don't
receive arguments.
Added some prototypes to radeon.h, and major reorder on radeon.h
adding prototypes in alphabetical order and specifying to file that
defines it.
diff --git a/src/ati.c b/src/ati.c
index b3f07ca..85da389 100644
--- a/src/ati.c
+++ b/src/ati.c
@@ -102,7 +102,7 @@ ati_device_get_from_busid(int bus, int dev, int func)
}
static struct pci_device*
-ati_device_get_primary()
+ati_device_get_primary(void)
{
struct pci_device *device = NULL;
struct pci_device_iterator *device_iter;
diff --git a/src/ati.h b/src/ati.h
index 828aae1..fa2e45e 100644
--- a/src/ati.h
+++ b/src/ati.h
@@ -31,4 +31,6 @@
#include "xf86_OSproc.h"
+extern void ati_gdev_subdriver(pointer options);
+
#endif /* ___ATI_H___ */
diff --git a/src/atimodule.c b/src/atimodule.c
index c249333..f0eb147 100644
--- a/src/atimodule.c
+++ b/src/atimodule.c
@@ -27,8 +27,6 @@
#include "ati.h"
#include "ativersion.h"
-extern void ati_gdev_subdriver(pointer options);
-
/* Module loader interface */
static XF86ModuleVersionInfo ATIVersionRec =
diff --git a/src/legacy_output.c b/src/legacy_output.c
index 0de13df..9dc7286 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -675,9 +675,9 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
unsigned long tmp;
RADEONOutputPrivatePtr radeon_output;
int tv_dac_change = 0, o;
- radeon_output = output->driver_private;
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ radeon_output = output->driver_private;
for (o = 0; o < xf86_config->num_output; o++) {
if (output == xf86_config->output[o]) {
break;
diff --git a/src/radeon.h b/src/radeon.h
index 8ebb3b3..f3db451 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -766,147 +766,204 @@ do { \
info->fifo_slots -= entries; \
} while (0)
-extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn);
-extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries);
-extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn);
+/* legacy_crtc.c */
+extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode);
+extern void legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
+ DisplayModePtr adjusted_mode, int x, int y);
+extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn);
+extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore);
+extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore);
+extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore);
+extern void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore);
+extern void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore);
+extern void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save);
+
+/* legacy_output.c */
+extern RADEONMonitorType legacy_dac_detect(ScrnInfoPtr pScrn,
+ xf86OutputPtr output);
+extern void legacy_output_dpms(xf86OutputPtr output, int mode);
+extern void legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
+ DisplayModePtr adjusted_mode);
+extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr);
+extern Bool RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch);
+extern Bool RADEONDVOWriteByte(I2CDevPtr dvo, int addr, CARD8 ch);
+extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
+extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
+extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore);
+extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
+extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
+extern void RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+
+/* radeon_accel.c */
+extern Bool RADEONAccelInit(ScreenPtr pScreen);
+extern void RADEONEngineFlush(ScrnInfoPtr pScrn);
+extern void RADEONEngineInit(ScrnInfoPtr pScrn);
+extern void RADEONEngineReset(ScrnInfoPtr pScrn);
+extern void RADEONEngineRestore(ScrnInfoPtr pScrn);
+extern CARD8 *RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp,
+ unsigned int w, CARD32 dstPitchOff,
+ CARD32 *bufPitch, int x, int *y,
+ unsigned int *h, unsigned int *hpass);
+extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn,
+ unsigned int bpp,
+ CARD8 *dst, CARD8 *src,
+ unsigned int hpass,
+ unsigned int dstPitch,
+ unsigned int srcPitch);
+extern void RADEONCopySwap(CARD8 *dst, CARD8 *src, unsigned int size, int swap);
+extern void RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst,
+ CARD32 pitch, int cpp,
+ CARD32 *dstPitchOffset, int *x, int *y);
+extern void RADEONInit3DEngine(ScrnInfoPtr pScrn);
+extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries);
#ifdef XF86DRI
-extern int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value);
-extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn);
+extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn);
+extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard);
+extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn);
+extern int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info);
+# ifdef USE_XAA
+extern Bool RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen);
+# endif
#endif
-extern void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y,
- Bool clone);
-
-extern void RADEONEngineReset(ScrnInfoPtr pScrn);
-extern void RADEONEngineFlush(ScrnInfoPtr pScrn);
-extern void RADEONEngineRestore(ScrnInfoPtr pScrn);
+#ifdef USE_XAA
+/* radeon_accelfuncs.c */
+extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a);
+extern Bool RADEONSetupMemXAA(int scrnIndex, ScreenPtr pScreen);
+#endif
-extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr);
-extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data);
+/* radeon_bios.c */
+extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10);
+extern Bool RADEONGetClockInfoFromBIOS(ScrnInfoPtr pScrn);
+extern Bool RADEONGetConnectorInfoFromBIOS(ScrnInfoPtr pScrn);
+extern Bool RADEONGetDAC2InfoFromBIOS(xf86OutputPtr output);
+extern Bool RADEONGetExtTMDSInfoFromBIOS(xf86OutputPtr output);
+extern Bool RADEONGetHardCodedEDIDFromBIOS(xf86OutputPtr output);
+extern Bool RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn);
+extern Bool RADEONGetLVDSInfoFromBIOS(xf86OutputPtr output);
+extern Bool RADEONGetTMDSInfoFromBIOS(xf86OutputPtr output);
+extern Bool RADEONGetTVInfoFromBIOS(xf86OutputPtr output);
+extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output);
+extern Bool RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn);
+
+/* radeon_commonfuncs.c */
+#ifdef XF86DRI
+extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn);
+#endif
+extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn);
-extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr);
-extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data);
+/* radeon_crtc.c */
+extern void radeon_crtc_load_lut(xf86CrtcPtr crtc);
+extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask);
+extern void RADEONBlank(ScrnInfoPtr pScrn);
+extern void RADEONComputePLL(RADEONPLLPtr pll, unsigned long freq,
+ CARD32 *chosen_dot_clock_freq,
+ CARD32 *chosen_feedback_div,
+ CARD32 *chosen_reference_div,
+ CARD32 *chosen_post_div, int flags);
+extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc,
+ DisplayModePtr pMode);
+extern void RADEONUnblank(ScrnInfoPtr pScrn);
+extern Bool RADEONSetTiling(ScrnInfoPtr pScrn);
+
+/* radeon_cursor.c */
+extern Bool RADEONCursorInit(ScreenPtr pScreen);
+extern void radeon_crtc_hide_cursor(xf86CrtcPtr crtc);
+extern void radeon_crtc_load_cursor_argb(xf86CrtcPtr crtc, CARD32 *image);
+extern void radeon_crtc_set_cursor_colors(xf86CrtcPtr crtc, int bg, int fg);
+extern void radeon_crtc_set_cursor_position(xf86CrtcPtr crtc, int x, int y);
+extern void radeon_crtc_show_cursor(xf86CrtcPtr crtc);
+
+/* radeon_dga.c */
+extern Bool RADEONDGAInit(ScreenPtr pScreen);
-extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn);
-extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn);
+#ifdef XF86DRI
+/* radeon_dri.c */
+extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen);
+extern void RADEONDRICloseScreen(ScreenPtr pScreen);
+extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen);
+extern int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn);
+extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn);
+extern void RADEONDRIResume(ScreenPtr pScreen);
+extern Bool RADEONDRIScreenInit(ScreenPtr pScreen);
+extern int RADEONDRISetParam(ScrnInfoPtr pScrn,
+ unsigned int param, int64_t value);
+extern Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on);
+extern void RADEONDRIStop(ScreenPtr pScreen);
+#endif
-extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn);
+/* radeon_driver.c */
+extern void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool clone);
+extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn);
+extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn);
+extern int RADEONMinBits(int val);
+extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr);
+extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr);
+extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data);
+extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data);
+extern void RADEONPllErrataAfterData(RADEONInfoPtr info);
+extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info);
+extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn);
+extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn);
-extern Bool RADEONAccelInit(ScreenPtr pScreen);
#ifdef USE_EXA
-extern Bool RADEONSetupMemEXA (ScreenPtr pScreen);
-extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen);
-#ifdef XF86DRI
-extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix);
-extern Bool RADEONGetDatatypeBpp(int bpp, CARD32 *type);
-extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix,
- CARD32 *pitch_offset);
-extern Bool RADEONDrawInitCP(ScreenPtr pScreen);
-extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn,
- CARD32 src_pitch_offset,
- CARD32 dst_pitch_offset,
- CARD32 datatype, int rop,
- Pixel planemask);
-extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX,
- int dstY, int w, int h);
-#endif
+/* radeon_exa.c */
+extern Bool RADEONSetupMemEXA(ScreenPtr pScreen);
+
+/* radeon_exa_funcs.c */
+extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX,
+ int dstY, int w, int h);
+extern void RADEONCopyMMIO(PixmapPtr pDst, int srcX, int srcY, int dstX,
+ int dstY, int w, int h);
+extern Bool RADEONDrawInitCP(ScreenPtr pScreen);
+extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen);
+extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn,
+ CARD32 src_pitch_offset,
+ CARD32 dst_pitch_offset,
+ CARD32 datatype, int rop,
+ Pixel planemask);
+extern void RADEONDoPrepareCopyMMIO(ScrnInfoPtr pScrn,
+ CARD32 src_pitch_offset,
+ CARD32 dst_pitch_offset,
+ CARD32 datatype, int rop,
+ Pixel planemask);
#endif
-#ifdef USE_XAA
-extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a);
-#endif
-extern void RADEONEngineInit(ScrnInfoPtr pScrn);
-extern Bool RADEONCursorInit(ScreenPtr pScreen);
-extern Bool RADEONDGAInit(ScreenPtr pScreen);
-
-extern void RADEONInit3DEngine(ScrnInfoPtr pScrn);
-
-extern int RADEONMinBits(int val);
-
-extern void RADEONInitVideo(ScreenPtr pScreen);
-extern void RADEONResetVideo(ScrnInfoPtr pScrn);
-extern void R300CGWorkaround(ScrnInfoPtr pScrn);
-
-extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info);
-extern void RADEONPllErrataAfterData(RADEONInfoPtr info);
-
-extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10);
-extern Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn);
-extern Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn);
-extern Bool RADEONGetLVDSInfoFromBIOS (xf86OutputPtr output);
-extern Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output);
-extern Bool RADEONGetTVInfoFromBIOS (xf86OutputPtr output);
-extern Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output);
-extern Bool RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output);
-
-extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-
-extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn);
-extern Bool RADEONI2cInit(ScrnInfoPtr pScrn);
-extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn);
-extern void RADEONPrintPortMap(ScrnInfoPtr pScrn);
-extern void RADEONDisableDisplays(ScrnInfoPtr pScrn);
-extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn);
-extern void RADEONUnblank(ScrnInfoPtr pScrn);
-extern void RADEONUnblank(ScrnInfoPtr pScrn);
-extern void RADEONBlank(ScrnInfoPtr pScrn);
-extern Bool RADEONSetTiling(ScrnInfoPtr pScrn);
-extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask);
-extern Bool RADEONAllocateConnectors(ScrnInfoPtr pScrn);
-extern void RADEONSetPitch (ScrnInfoPtr pScrn);
-extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode);
-
-extern DisplayModePtr
-RADEONProbeOutputModes(xf86OutputPtr output);
-
-extern Bool
-RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch);
-extern Bool
-RADEONDVOWriteByte(I2CDevPtr dvo, int addr, CARD8 ch);
-extern Bool
-RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output);
-extern Bool
-RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output);
-
-extern RADEONI2CBusRec
-legacy_setup_i2c_bus(int ddc_line);
-extern RADEONI2CBusRec
-atom_setup_i2c_bus(int ddc_line);
-
-extern void
-radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y);
-extern void
-radeon_crtc_show_cursor (xf86CrtcPtr crtc);
-extern void
-radeon_crtc_hide_cursor (xf86CrtcPtr crtc);
-extern void
-radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y);
-extern void
-radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg);
-extern void
-radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image);
-extern void
-radeon_crtc_load_lut(xf86CrtcPtr crtc);
+#if defined(XF86DRI) && defined(USE_EXA)
+/* radeon_exa.c */
+extern Bool RADEONGetDatatypeBpp(int bpp, CARD32 *type);
+extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix,
+ CARD32 *pitch_offset);
+extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix);
+#endif
+/* radeon_modes.c */
+extern void RADEONSetPitch(ScrnInfoPtr pScrn);
+extern DisplayModePtr RADEONProbeOutputModes(xf86OutputPtr output);
+
+/* radeon_output.c */
+extern RADEONI2CBusRec atom_setup_i2c_bus(int ddc_line);
+extern RADEONI2CBusRec legacy_setup_i2c_bus(int ddc_line);
+extern void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output);
+extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn);
+extern void RADEONInitConnector(xf86OutputPtr output);
+extern void RADEONPrintPortMap(ScrnInfoPtr pScrn);
+extern void RADEONSetOutputType(ScrnInfoPtr pScrn,
+ RADEONOutputPrivatePtr radeon_output);
+extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn);
+
+/* radeon_tv.c */
+extern void RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
DisplayModePtr mode, xf86OutputPtr output);
extern void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
@@ -917,47 +974,18 @@ extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save
DisplayModePtr mode, xf86OutputPtr output);
extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
DisplayModePtr mode, BOOL IsPrimary);
-
extern void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
+extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode);
-extern void RADEONComputePLL(RADEONPLLPtr pll, unsigned long freq, CARD32 *chosen_dot_clock_freq,
- CARD32 *chosen_feedback_div, CARD32 *chosen_reference_div,
- CARD32 *chosen_post_div, int flags);
+/* radeon_video.c */
+extern void RADEONInitVideo(ScreenPtr pScreen);
+extern void RADEONResetVideo(ScrnInfoPtr pScrn);
#ifdef XF86DRI
-#ifdef USE_XAA
-extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a);
-#endif
-extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn);
-extern Bool RADEONDRIScreenInit(ScreenPtr pScreen);
-extern void RADEONDRICloseScreen(ScreenPtr pScreen);
-extern void RADEONDRIResume(ScreenPtr pScreen);
-extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen);
-extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen);
-extern int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn);
-extern void RADEONDRIStop(ScreenPtr pScreen);
-
-extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn);
-extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard);
-extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn);
-extern int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info);
-extern Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on);
-
-extern void RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst,
- CARD32 pitch, int cpp,
- CARD32 *dstPitchOffset, int *x, int *y);
-extern CARD8* RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp,
- unsigned int w, CARD32 dstPitchOff,
- CARD32 *bufPitch, int x, int *y,
- unsigned int *h, unsigned int *hpass);
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