Bug#686949: ITP: fpgatools -- A small independent command line FPGA utilities, no GUI plain C, text-based file formats. convert floorplan from/to bitstream.
Timo,
sure I can and love to comment, thanks for asking.
The state of fpgatools is 'alpha' today, not much is working
yet. But I keep working on it every day. Xiangfu is helping me
with the Debian packaging early because in the past we learned
it sometimes takes years (yes :-)) to make it through all the
various requirements and issues before packages really arrive
in unstable etc. Nothing wrong with high quality but we wanted
to start early this time.
At this moment I am writing the 'hello world' app, which will
be the first simple design that the tools can generate, load
into a xc6slx9 and run there.
> > * VHDL/verilog compiler to netlist
> > * place and route tool to turn the netlist into a floorplan
> >
> > Is this correct?
>
> Wolfgang, can you comment on this? You can read the full discussion at
I am in the fpga area for a number of years, and numerous tools
exist. fpgatools tries to focus on one of the core missing bits,
which is the bitstream file format.
The way to generate a bitstream right now (as you can see in
the hello world app in a few days), is to link against the libfpga
apis and call apis to fill the chip's resources and routing.
Then instantiate (write) the floorplan/bitstream from memory.
My goal is to make that work really well which will take a few
months. A verilog backend can be added later, but I don't plan
to do that until I have really addressed the chip's features well.
Right now I support maybe 1% of the chip's features...
Most likely the verilog backend would be reactivated in iverilog,
where an 'fpga' target exists but is dormant the last few years.
So my idea was (at that point) to go to iverilog and bring the
fpga target back, and use libfpga in that target to generate
floorplans/bitstreams.
iverilog would then provide a means to program an fpga via
Verilog.
Another potential is that I will first write a small bison
parser as part of fpgatools, then iverilog/verilog later.
So, three steps:
1) program with C api by linking against libfpga to write bitstream
- you can see how this works in fpgatools' "hello world"
app in a few days
2) program with bison-parsed 'new' language that plugs into libfpga
3) program with reactivated iverilog fpga backend
Most likely they will appear in that order, and I will be exclusively
on #1 for at least several more months. If someone wants to join and
start in the iverilog backend today, that would be great of course.
Hope this explains. THANKS FOR ASKING, Cheers,
Wolfgang
On Tue, Sep 18, 2012 at 04:01:25PM +0300, Timo Juhani Lindfors wrote:
> Hi,
>
> > I had a quick look at the tools. They convert a floorplan description
> > into a bitstream and back. However for a complete workflow the
> > following bits are missing:
> >
> > * VHDL/verilog compiler to netlist
> > * place and route tool to turn the netlist into a floorplan
> >
> > Is this correct?
>
> Wolfgang, can you comment on this? You can read the full discussion at
>
> http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=686949
>
>
> best regards,
> Timo Lindfors
Reply to: