Re: Resolved - was [Re: Identifying CPU]

[Stan Hoeppner <stan@hardwarefreak.com>]

On 9/1/2013 8:09 AM, Richard Owlett wrote:
> Stan Hoeppner wrote:
>> On 8/31/2013 10:00 AM, Richard Owlett wrote:
>>
>>> Especially as I explicitly emphasized wanting to know bus width.
>>
>> I find it curious Richard that you emphasize this, given that the "CPU
>> bus width" in isolation is meaningless.
>>
>> Every x86 CPU since the original Pentium that shipped in 1993, up to the
>> Opteron which shipped in 2003, had a 64 bit wide data bus, clocked from
>> 66 to 266MHz, including double/quad pumped buses.  Throughput has varied
>> from the first to the last model from 528MB/s to 8.5GB/s.
>>
>> In the post Opteron era the memory buses are decoupled from the system
>> interconnect, the latter no longer being a bus but a apir of
>> bidirectional point-point serial links.  Modern CPUs have 2 to 4x 64bit
>> wide memory buses clocked at up to 1600 MHz, for a combined DRAM
>> bandwidth of 25.6 to 51.2GB/s.  The system interconnect links,
>> HyperTransport in the case of AMD CPUs, provide from 3.2GB/s to 12.8GB/s
>> one way.
>>
>> On CPUs shipped since 2003 in the case of AMD, later for Intel, there is
>> no singular "bus width".  There are 2, 3, or 4 memory buses, and a
>> system interconnect, all clocked at different speeds on different vendor
>> models.
>>
>> So I fail to see why your knowing the "CPU bus width" is relevant to
>> anything.
>>
> 
> 'Cause I'm so old I remember introduction of 8085 and a Z80A was
> considered a speed demon at 2 MHz ;/
> 
> If I understand correctly some processors can run 32 bit OSes but not
> any 64 bit OS.

You're confusing register width with data bus width.  Register width
dictates which binary instruction sets can be executed.

The width of the data bus(es) simply dictates how much data you can move
per unit time to DRAM and peripherals.  There is no correlation between
register width and data bus width.

Using examples from an era that you're more familiar with, the Intel
8086 had a 16 bit register width and a 16 bit data bus to the system.
Intel shortly thereafter released the 8088 which ditched the 16 bit data
bus for an 8 bit bus.  This was done to reduce the cost of the system,
and as a result reduced IO performance by 50%.  Intel did this again
with the 80386sx, taking the 80386 CPU with a 32 bit register width and
a 32 bit data bus, and reducing the data bus to 16 bits, again to reduce
system costs.

-- 
Stan