Makefile question??

[ISHWAR RATTAN <rattan@cps.cmich.edu>]

CC   = gcc
SRCS = a.c b1.c c1.c
OBJS = $(addsuffix .o, $(basename $(SRCS) .c))

target: $(OBJS)
	$(CC) $(LDFLAGS) $(OBJS) -o target

somehow make does not like the line that sets up OBJS
says that no rules to make target found but if replaced
as
OBJS = a.o b1.o c1.o

it works!

Any pointers?
-ishwar