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Re: make problem



On 07/23/2006 06:23 AM, Fred J. wrote:
[...]
these 2 lines put all the .cpp and .o files in the current directory
in the variables SRC and OBJ respectively.
SRC := $(wildcard *.cpp)
OBJ := $(wildcard *.o)


this line is the compiler section which uses g++ to compile all the
.cpp and .h (assuming #include directives are correct) into .o files
proj: $(SRC)
    $(CXX) -Wall -I/usr/include -c $^

this line links all those .o files that were generated from the
compilation command above
#### linker section ####
proj: $(OBJ)
    $(CXX) -L/usr/local/lib $^ -lgsl -lgslcblas -lm
[...]

Make doesn't know which set of rules to use the make the target 'proj.' If you want to have two rules with the same target name in gnu-make, they must both be double-colon rules, but that's probably not what you need here.

Instead, you evidently want to not have to list each source file and object file by name in the makefile, and that's fine so long as you follow make's rules.

Remove the first 'proj' target and replace it with a pattern rule that creates %.o files from %.cpp files.

And the OBJ variable should use the list of .cpp files to create a list of .o files:

OBJ := $(subst .cpp, .o, $(SRC))

It's been a while since I've done makefiles, but I do remember having to do things like this.

HTH

P.S.
It's a good idea to specify the target when creating the executable using '-o $@'.




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