Re: Amount of RAM L1 cache on a processor will support
Thanks to Aaron, Nate, dman, and Gary, especially for the web page
references. I'll spend some time looking at that before asking
again.
Your articles were enlightening, but you don't address my question.
I know only 256 or 384 K will be in the cache at anyone time.
I also know that the tag ram is what determines how much of memory
can be cached (paged against with the pages of cache, done EXACTLY
like the disk is paged against main memory.)
I have spent considerable time pouring over google references and
have found Alan Cox's article about the issue of a machine having
too little tag ram. I also found articles about the 430 chip set and
the tag ram having 8 bits restricting maximum cacheable memory to
what? 64MB and 11 bits restricting to some larger number.
I was once able to do the necessary computations, but I last taught
architecture several years ago. I still have the broad brush strokes
of the ideas, but no details.
I went to AMDs web site and looked at the documents for the Athlon.
They say the chip has 256K of "L2" cache. That cache is still on
chip, and I prefere to call that "L1", and I prefer to call the data
stream cache and instruction stream cache just that, instruction
cache and data cache.
Incidentaily I don't understand how the instruction cache or data
cache can be thought of as caching against main memory. According to
the diagrams in the article from AMD what they call "L1" cache is
used to cache data and instructions from the L2 cache which in turn
actually caches against main memory.
The article says "that the L2 cache being on the processor makes the
maximum cacheable memory 'non-issue'." I find that hard to believe,
unless there is something about the architecture the author isn't
saying.
The bottom line is that they say exactly zip about the tag ram. How
the blazes do I find out how big the cache pages are and how much
tag ram the Athlon cache has? Once i know these bits of data I can
determine how much RAM the blankety blank thing will cache.
The MoBo uses 266 MHz front side bus, and the DDR (double data rate)
RAM is 266 MHz (unless there something else I either never knew or
have forgotton) That suggests to me that the whole of memory is as
fast as some early caches were. I suspect that is colored marketoid
too.
Oh well, if you know anything else that you can tell me, including
where to look please, send email!
Again thanks for the assistance. I have several places to look I did
not have earlier. This community is the greatest.
--David
[On Wed, 12 Dec 2001, Aaron Traas wrote:
> I don't know how to answer the question you asked, but there is
> something you need to consider. Assuming you have an Athlon of the
> Thunderbird core or later, you have:
>
> 128K of L1 cache
> 256K of L2 cache
>
> Most CPU's use an inclusive cache mechanism. What this means is that all
> data stored in the L1 cache is also mirrored in L2. This makes it easier
> to do a fetch; when data is fetched into cache, it is placed into L2.
> When a smaller subset is requested, it goes from L2 into L1, leaving a
> copy in L2.
>
> With the Thunderbird core, AMD switched over to using an exclusive cache
> mechanism. I.E., the data in L1 is NOT mirrored in L2. Thus, you have
> 384K of usable cache, and the differentiation of L1 and L2 is just for
> speed. Things get swapped between L1 and L2 as needed, but you really
> have 384K of cache to work with. That gives you more cacheable mem than
> you would with an inclusive system.
>
> Now, with a mere 512MB of RAM on a very modern system, you should be
> fine. Most modern systems can handle > 1GB without having caching
> problems. There are some speed issues to worry about, however; Most
> larger DIMMs are slower than smaller DIMMs. For instance, most 512MB
> DIMMs are registered, which is slower than unbuffered. Most 512MB DIMMs
> have a CAS latency of 3 (CAS = Column Access Strobe), while many smaller
> DIMMs are rated at CAS 2. There are also signal integrigty issues with
> having 3 or more double-sided DIMMs on the same Mobo (case in point, the
> nForce chipset goes into "SuperStability Mode" if there is a
> double-sided DIMM in the third slot, which turns down performance a
> great deal to keep from becoming unstable.)
>
> I'm sorry if this answer was more than you bargained for, but I'm known
> among friends for not being able to give simple answers :)
>
> --Aaron
>
> David Teague wrote:
> >
> > If you put more RAM in a computer system than the caching system
> > will suppport, the system will run more slowly than it would with
> > less RAM. IF I understand correctly, the amount of RAM depends on
> > the amount of tag RAM.
> >
> > I have 512 MB on my Abit MoBo with a 1GHz Athlon.
> >
> > How do I determine how much RAM the L1 cache in a 1GHz Athlon will
> > support?
> >
> > --David
> > David Teague, dbt@cs.wcu.edu
> > Debian GNU/Linux Because software support is free, timely,
> > useful, technically accurate, and friendly.
> > (I hope this is all of the above.)
> >
> > --
> > To UNSUBSCRIBE, email to debian-user-request@lists.debian.org
> > with a subject of "unsubscribe". Trouble? Contact listmaster@lists.debian.org
>
--David
David Teague, dbt@cs.wcu.edu
Debian GNU/Linux Because software support is free, timely,
useful, technically accurate, and friendly.
(I hope this is all of the above.)
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