Re: Zicntr / Debian/riscv64: rdcycle causing Illegal instruction
Hi,
On 2022-09-01 13:49, Mathieu Malaterre wrote:
> Hi all,
>
> On Thu, Sep 1, 2022 at 9:11 AM Mathieu Malaterre <malat@debian.org> wrote:
> >
> > Aurélien,
> >
> > If you still have some time, could you dump more info:
> >
> > ---------- Forwarded message ---------
> >
> > Is it possible to debug and see the $mepc, $mcause and $mtval at the
> > point at which the fault occurs? That might shed some light on the
> > reason for this issue.
The reason is the one pointed by Jessica, scounteren is set to 0x2,
disabling access to the rdcycle instruction from userland. This happens
due to the SBI PMU support which has been added in Linux version 5.18
[1] in the pmu_sbi_starting_cpu() function [2].
To trigger the bug you therefore need 1) kernel >= 5.18 2) an SBI
implementation with PMU support.
> Discussing the issue with upstream lead to the following patch (*).
> Important part pasted here:
>
> [...]
> -#elif HWY_ARCH_RVV
> + // TODO(janwas): the cycle counter and even the timer CSR are no
> longer in the
> + // base spec and are part of the Zicntr extension, which is not yet ratified
> + // as of 2022-09
> +#elif HWY_ARCH_RVV && defined(__riscv_zicntr)
> asm volatile("rdcycle %0" : "=r"(t));
> [...]
It doesn't look correct to me. It might hide the issue for now. However
once the Zicntr extension get ratified, it will likely be included in
the RV64GC baseline, and thus the compiler will define __riscv_zicntr:
this will fail again the same way.
Cheers
Aurelien
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e9991434596f5373dfd75857b445eb92a9253c56
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/perf/riscv_pmu_sbi.c?id=2880e1a175b9f31798f9d9482ee49187f61b5539#n649
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
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