Zicntr / Debian/riscv64: rdcycle causing Illegal instruction
Hi all,
On Thu, Sep 1, 2022 at 9:11 AM Mathieu Malaterre <malat@debian.org> wrote:
>
> Aurélien,
>
> If you still have some time, could you dump more info:
>
> ---------- Forwarded message ---------
>
> Is it possible to debug and see the $mepc, $mcause and $mtval at the
> point at which the fault occurs? That might shed some light on the
> reason for this issue.
Discussing the issue with upstream lead to the following patch (*).
Important part pasted here:
[...]
-#elif HWY_ARCH_RVV
+ // TODO(janwas): the cycle counter and even the timer CSR are no
longer in the
+ // base spec and are part of the Zicntr extension, which is not yet ratified
+ // as of 2022-09
+#elif HWY_ARCH_RVV && defined(__riscv_zicntr)
asm volatile("rdcycle %0" : "=r"(t));
[...]
Maybe it will make sense to someone (**).
-M
(*) https://github.com/google/highway/commit/1911baef8c8edf58d99fafd53de433d11837f08c.patch
(**) [RFC] zicntr and zihpm issues and how to deal with future ISA
spec changes in future?
https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/QKjQhChrq9Q
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