Re: Packaging of the RISC-V ecosystem?
On Wed, Nov 09, 2016 at 09:55:25AM +0800, Paul Wise wrote:
> I wonder how much of the RISC-V ecosystem we should include within Debian.
>
> Presumably we want a Linux riscv64el port and the associated
> bootloader, kernel and toolchain support.
Yes.
> Presumably we eventually want qemu user and system support, both
> hardware accelerated native and emulated.
Regular qemu system and user support: definitely yes.
There is no hardware-accelerated native qemu support yet :-).
> Perhaps we want bare-metal cross-toolchains for non-64-bit RISC-V
> CPUs? This would be useful for compiling firmware for the lowRISC
> minion cores I guess.
>
> Maybe we want hardware development tools like the Chisel hardware
> description language, the Spike simulator and so on?
>
> Do we want some of the open CPU cores packaged and built for the FPGA
> architectures with libre toolchains?
A bare-metal toolchain makes sense at least as far as it targets
the LowRISC minion cores which will probably be PULPino-based and
therefore effectively RV32I-only. AFAIK The PULPino implements
hardware multiply but not hardware division, so code for it
cannot be built with a compiler targeting full RV32IM.
Information about the Pulpino from the 3rd RISC-V workshop:
https://riscv.org/wp-content/uploads/2016/01/Wed1315-PULP-riscv3_noanim.pdf
Bare-metal toolchains besides the one necessary for building the
minion-core firmware would IMHO be nice-to-have but optional. A
potentially interesting bare-metal target besides RV32I could be
RV32IM, which AFAIK can - in the form of a (BSD-licensed) ORCA
core - be implemented in a Lattice iCE40-8k FPGA. This is
insofar interesting as there is a free FPGA toolchain for this
type of FPGA in Debian.
Information about the ORCA core series from the 3rd RISC-V
workshop:
https://riscv.org/wp-content/uploads/2016/01/Wed1200-2016-01-05-VectorBlox-ORCA-RISC-V-DEMO.pdf
Regards,
Karsten
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