[Date Prev][Date Next] [Thread Prev][Thread Next] [Date Index] [Thread Index]

Re: Powerbook G4 1.33 GHz CPU temperature

More specifically...

PPLL_REF_DIV holds the reference divider for the pixel clock PLL
(though the register has a weird format on >= r300)

PPLL_DIV_{0..3} holds the forward and feedback dividers for that PLL,
(feedback divider in bits 0..10 and post div in bits 16..18)

the CLK_CNTL_INDEX bits 8..9 hold the selector for which PPPL_DIV_{0..3}
register holds the current value to use (also called ppll_div_sel)


Reply to: