[PATCH] Fix radeon support for LCD scaling
I think I fixed the support for scaling on flat panels with
radeonfb (and XFree using UseFBDev).
That mean you can now use non-native resolutions with an LCD
display (either internal LCD on laptop or external TFT) with
radeonfb. It may fix the problem some users are having with
MOL in console mode as well
(Note to Samuel: you may still want to add to molvconfig an
option to "pick" the current mode when launched which is typically
the panel "native" mode, at least until I add a way to retreive
that "native" mode via some ioctl).
Try the attached patch (against 2.4.20-ben9) and tell me if
it works, doesn't work, etc...
Ben.
diff -urN linux-2.4.20-ben9/drivers/video/radeon.h linuxppc_benh_stable/drivers/video/radeon.h
--- linux-2.4.20-ben9/drivers/video/radeon.h 2003-03-23 11:56:35.000000000 +0100
+++ linuxppc_benh_stable/drivers/video/radeon.h 2003-03-25 16:44:06.000000000 +0100
@@ -565,7 +565,7 @@
#define TMDS_PLL_EN (1 << 0)
#define TMDS_PLLRST (1 << 1)
#define TMDS_RAN_PAT_RST (1 << 7)
-#define ICHCSEL (1 << 28)
+#define TMDS_ICHCSEL (1 << 28)
/* FP_HORZ_STRETCH bit constants */
#define HORZ_STRETCH_RATIO_MASK 0xffff
diff -urN linux-2.4.20-ben9/drivers/video/radeonfb.c linuxppc_benh_stable/drivers/video/radeonfb.c
--- linux-2.4.20-ben9/drivers/video/radeonfb.c 2003-03-23 12:00:22.000000000 +0100
+++ linuxppc_benh_stable/drivers/video/radeonfb.c 2003-03-27 13:41:16.000000000 +0100
@@ -24,6 +24,15 @@
* 2002-09-21 rv250, r300, m9 initial support,
* added mirror option, 0.1.6
*
+ * Other change (--BenH)
+ *
+ * 2003-01-01 Tweaks for PLL on some iBooks
+ * 2003-01-01 Fix SURFACE_CNTL usage on r9000
+ * 2003-03-23 Added new Power Management code from ATI
+ * 2003-03-23 Added default PLL values for r300 from lkml
+ * 2003-03-26 Never set TMDS_PLL_EN, it seem to break more than
+ * just old r300's
+ *
* Special thanks to ATI DevRel team for their hardware donations,
* and for spending the time to fix the power management code !
*
@@ -37,7 +46,7 @@
*/
-#define RADEON_VERSION "0.1.6"
+#define RADEON_VERSION "0.1.6-ben"
#include <linux/config.h>
@@ -323,7 +332,8 @@
u32 crtc_gen_cntl;
u32 crtc_ext_cntl;
u32 dac_cntl;
-
+ u32 crtc_more_cntl;
+
u32 flags;
u32 pix_clock;
int xres, yres;
@@ -1410,6 +1420,16 @@
rinfo->pll.ref_div = 67;
rinfo->pll.ref_clk = 2700;
break;
+ case PCI_DEVICE_ID_ATI_RADEON_ND:
+ case PCI_DEVICE_ID_ATI_RADEON_NE:
+ case PCI_DEVICE_ID_ATI_RADEON_NF:
+ case PCI_DEVICE_ID_ATI_RADEON_NG:
+ rinfo->pll.ppll_max = 40000;
+ rinfo->pll.ppll_min = 20000;
+ rinfo->pll.xclk = 27000;
+ rinfo->pll.ref_div = 12;
+ rinfo->pll.ref_clk = 2700;
+ break;
}
printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d defaults\n",
@@ -2704,6 +2724,7 @@
/* CRTC regs */
save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
+ save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
save->dac_cntl = INREG(DAC_CNTL);
save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
@@ -2739,9 +2760,8 @@
hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
- u32 dotClock = 1000000000 / mode->pixclock,
- sync, h_sync_pol, v_sync_pol;
- unsigned int freq = dotClock / 10; /* x 100 */
+ u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
+ unsigned int freq;
unsigned int xclk_freq, vclk_freq;
int xclk_per_trans, xclk_per_trans_precise;
int useable_precision, roff, ron;
@@ -2763,7 +2783,8 @@
vSyncStart = mode->yres + mode->lower_margin;
vSyncEnd = vSyncStart + mode->vsync_len;
vTotal = vSyncEnd + mode->upper_margin;
-
+ pixClock = mode->pixclock;
+
if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
if (rinfo->panel_xres < mode->xres)
rinfo->xres = mode->xres = rinfo->panel_xres;
@@ -2777,7 +2798,11 @@
vTotal = mode->yres + rinfo->vblank;
vSyncStart = mode->yres + rinfo->vOver_plus;
vSyncEnd = vSyncStart + rinfo->vSync_width;
+
+ pixClock = 100000000 / rinfo->clock;
}
+ dotClock = 1000000000 / pixClock;
+ freq = dotClock / 10; /* x100 */
sync = mode->sync;
h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
@@ -2818,6 +2843,10 @@
newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
(format << 8);
+ /* Clear auto-center etc... */
+ newmode.crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
+ newmode.crtc_more_cntl &= 0xfffffff0;
+
if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
if (mirror)
@@ -2887,7 +2916,7 @@
rinfo->bpp = mode->bits_per_pixel;
rinfo->depth = depth;
- RTRACE("pixclock = %lu\n", (unsigned long)mode->pixclock);
+ RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
RTRACE("freq = %lu\n", (unsigned long)freq);
if (freq > rinfo->pll.ppll_max)
@@ -2971,13 +3000,14 @@
if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
unsigned int hRatio, vRatio;
+#if 0
/* We force the pixel clock to be always enabled. Allowing it
* to be power managed during blanking would save power, but has
* nasty interactions with the 2D engine & sleep code that haven't
* been solved yet. --BenH
*/
newmode.vclk_ecp_cntl &= ~PIXCLK_DAC_ALWAYS_ONb;
-
+#endif
if (mode->xres > rinfo->panel_xres)
mode->xres = rinfo->panel_xres;
if (mode->yres > rinfo->panel_yres)
@@ -3035,13 +3065,15 @@
} else {
/* DFP */
newmode.fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
- newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST | ICHCSEL) &
+ newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST | TMDS_ICHCSEL) &
~(TMDS_PLLRST);
+#if 0 /* Happens on r200 too, we disable that code for now and see... */
/* There is something wrong with setting TMDS_PLL_EN
* bit on older radeon's with ADC monitors
*/
if (rinfo->arch != RADEON_R100)
newmode.tmds_transmitter_cntl |= TMDS_PLL_EN;
+#endif
newmode.crtc_ext_cntl &= ~CRTC_CRT_ON;
}
@@ -3087,6 +3119,7 @@
OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
+ OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
@@ -3249,8 +3282,6 @@
#ifdef CONFIG_PMAC_PBOOK
-static u32 dbg_clk;
-
/*
* Radeon M6, M7 and M9 Power Management code. This code currently
* only supports the mobile chips in D2 mode, that is typically what
@@ -3375,22 +3406,22 @@
static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
{
/* Set v2clk to 65MHz */
- OUTPLL(pllPIXCLKS_CNTL, INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK );
+ OUTPLL(pllPIXCLKS_CNTL,
+ INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK);
OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
-
OUTPLL(pllP2PLL_CNTL, 0x0000bf00);
-
- OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W );
+ OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W);
- OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);
- mdelay( 1);
+ OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);
+ mdelay(1);
- OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET);
+ OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET);
mdelay( 1);
- OUTPLL(pllPIXCLKS_CNTL, (INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK) | (0x03 << PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT));
-
+ OUTPLL(pllPIXCLKS_CNTL,
+ (INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK)
+ | (0x03 << PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT));
mdelay( 1);
}
@@ -3418,7 +3449,7 @@
OUTREG(TV_DAC_CNTL, reg);
reg = INREG(TMDS_TRANSMITTER_CNTL);
- reg &= ~(TMDS_PLL_EN |TMDS_PLLRST);
+ reg &= ~(TMDS_PLL_EN | TMDS_PLLRST);
OUTREG(TMDS_TRANSMITTER_CNTL, reg);
reg = INREG(DAC_CNTL);
@@ -3450,33 +3481,32 @@
/* Force Core Clocks */
sclk_cntl = INPLL( pllSCLK_CNTL_M6);
- sclk_cntl |=
- SCLK_CNTL_M6__IDCT_MAX_DYN_STOP_LAT|
- SCLK_CNTL_M6__VIP_MAX_DYN_STOP_LAT|
- SCLK_CNTL_M6__RE_MAX_DYN_STOP_LAT|
- SCLK_CNTL_M6__PB_MAX_DYN_STOP_LAT|
- SCLK_CNTL_M6__TAM_MAX_DYN_STOP_LAT|
- SCLK_CNTL_M6__TDM_MAX_DYN_STOP_LAT|
- SCLK_CNTL_M6__RB_MAX_DYN_STOP_LAT|
-
- SCLK_CNTL_M6__FORCE_DISP2|
- SCLK_CNTL_M6__FORCE_CP|
- SCLK_CNTL_M6__FORCE_HDP|
- SCLK_CNTL_M6__FORCE_DISP1|
- SCLK_CNTL_M6__FORCE_TOP|
- SCLK_CNTL_M6__FORCE_E2|
- SCLK_CNTL_M6__FORCE_SE|
- SCLK_CNTL_M6__FORCE_IDCT|
- SCLK_CNTL_M6__FORCE_VIP|
-
- SCLK_CNTL_M6__FORCE_RE|
- SCLK_CNTL_M6__FORCE_PB|
- SCLK_CNTL_M6__FORCE_TAM|
- SCLK_CNTL_M6__FORCE_TDM|
- SCLK_CNTL_M6__FORCE_RB|
- SCLK_CNTL_M6__FORCE_TV_SCLK|
- SCLK_CNTL_M6__FORCE_SUBPIC|
- SCLK_CNTL_M6__FORCE_OV0;
+ sclk_cntl |= SCLK_CNTL_M6__IDCT_MAX_DYN_STOP_LAT|
+ SCLK_CNTL_M6__VIP_MAX_DYN_STOP_LAT|
+ SCLK_CNTL_M6__RE_MAX_DYN_STOP_LAT|
+ SCLK_CNTL_M6__PB_MAX_DYN_STOP_LAT|
+ SCLK_CNTL_M6__TAM_MAX_DYN_STOP_LAT|
+ SCLK_CNTL_M6__TDM_MAX_DYN_STOP_LAT|
+ SCLK_CNTL_M6__RB_MAX_DYN_STOP_LAT|
+
+ SCLK_CNTL_M6__FORCE_DISP2|
+ SCLK_CNTL_M6__FORCE_CP|
+ SCLK_CNTL_M6__FORCE_HDP|
+ SCLK_CNTL_M6__FORCE_DISP1|
+ SCLK_CNTL_M6__FORCE_TOP|
+ SCLK_CNTL_M6__FORCE_E2|
+ SCLK_CNTL_M6__FORCE_SE|
+ SCLK_CNTL_M6__FORCE_IDCT|
+ SCLK_CNTL_M6__FORCE_VIP|
+
+ SCLK_CNTL_M6__FORCE_RE|
+ SCLK_CNTL_M6__FORCE_PB|
+ SCLK_CNTL_M6__FORCE_TAM|
+ SCLK_CNTL_M6__FORCE_TDM|
+ SCLK_CNTL_M6__FORCE_RB|
+ SCLK_CNTL_M6__FORCE_TV_SCLK|
+ SCLK_CNTL_M6__FORCE_SUBPIC|
+ SCLK_CNTL_M6__FORCE_OV0;
OUTPLL( pllSCLK_CNTL_M6, sclk_cntl);
@@ -3497,8 +3527,6 @@
);
OUTPLL( pllMCLK_CNTL_M6, mclk_cntl);
-
-
/* Force Display clocks */
vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL);
vclk_ecp_cntl &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
@@ -3508,12 +3536,12 @@
pixclks_cntl = INPLL( pllPIXCLKS_CNTL);
pixclks_cntl &= ~( PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
- PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
- PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
- PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
- PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
- PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
- PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
+ PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
+ PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
+ PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
+ PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
+ PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
+ PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);
@@ -3523,34 +3551,33 @@
pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL);
pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__SPLL_TURNOFF |
- PLL_PWRMGT_CNTL__MPLL_TURNOFF|
- PLL_PWRMGT_CNTL__PPLL_TURNOFF|
- PLL_PWRMGT_CNTL__P2PLL_TURNOFF|
- PLL_PWRMGT_CNTL__TVPLL_TURNOFF;
+ PLL_PWRMGT_CNTL__MPLL_TURNOFF|
+ PLL_PWRMGT_CNTL__PPLL_TURNOFF|
+ PLL_PWRMGT_CNTL__P2PLL_TURNOFF|
+ PLL_PWRMGT_CNTL__TVPLL_TURNOFF;
OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL_M6);
clk_pwrmgt_cntl &= ~( CLK_PWRMGT_CNTL_M6__MPLL_PWRMGT_OFF|
- CLK_PWRMGT_CNTL_M6__SPLL_PWRMGT_OFF|
- CLK_PWRMGT_CNTL_M6__PPLL_PWRMGT_OFF|
- CLK_PWRMGT_CNTL_M6__P2PLL_PWRMGT_OFF|
- CLK_PWRMGT_CNTL_M6__MCLK_TURNOFF|
- CLK_PWRMGT_CNTL_M6__SCLK_TURNOFF|
- CLK_PWRMGT_CNTL_M6__PCLK_TURNOFF|
- CLK_PWRMGT_CNTL_M6__P2CLK_TURNOFF|
- CLK_PWRMGT_CNTL_M6__TVPLL_PWRMGT_OFF|
- CLK_PWRMGT_CNTL_M6__GLOBAL_PMAN_EN|
- CLK_PWRMGT_CNTL_M6__ENGINE_DYNCLK_MODE|
- CLK_PWRMGT_CNTL_M6__ACTIVE_HILO_LAT_MASK|
- CLK_PWRMGT_CNTL_M6__CG_NO1_DEBUG_MASK
- );
+ CLK_PWRMGT_CNTL_M6__SPLL_PWRMGT_OFF|
+ CLK_PWRMGT_CNTL_M6__PPLL_PWRMGT_OFF|
+ CLK_PWRMGT_CNTL_M6__P2PLL_PWRMGT_OFF|
+ CLK_PWRMGT_CNTL_M6__MCLK_TURNOFF|
+ CLK_PWRMGT_CNTL_M6__SCLK_TURNOFF|
+ CLK_PWRMGT_CNTL_M6__PCLK_TURNOFF|
+ CLK_PWRMGT_CNTL_M6__P2CLK_TURNOFF|
+ CLK_PWRMGT_CNTL_M6__TVPLL_PWRMGT_OFF|
+ CLK_PWRMGT_CNTL_M6__GLOBAL_PMAN_EN|
+ CLK_PWRMGT_CNTL_M6__ENGINE_DYNCLK_MODE|
+ CLK_PWRMGT_CNTL_M6__ACTIVE_HILO_LAT_MASK|
+ CLK_PWRMGT_CNTL_M6__CG_NO1_DEBUG_MASK
+ );
clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL_M6__GLOBAL_PMAN_EN | CLK_PWRMGT_CNTL_M6__DISP_PM;
- OUTPLL( pllCLK_PWRMGT_CNTL_M6, clk_pwrmgt_cntl);
-
+ OUTPLL( pllCLK_PWRMGT_CNTL_M6, clk_pwrmgt_cntl);
clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
@@ -3560,7 +3587,9 @@
/* AGP PLL control */
OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | BUS_CNTL1__AGPCLK_VALID);
- OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK) | (2<<BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT)); // 440BX
+ OUTREG(BUS_CNTL1,
+ (INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK)
+ | (2<<BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT)); // 440BX
OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL) & ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN));
clk_pin_cntl &= ~CLK_PIN_CNTL__CG_CLK_TO_OUTPIN;
@@ -3568,7 +3597,9 @@
OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
/* Solano2M */
- OUTREG(AGP_CNTL, (INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK)) | (0x20<<AGP_CNTL__MAX_IDLE_CLK__SHIFT));
+ OUTREG(AGP_CNTL,
+ (INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK))
+ | (0x20<<AGP_CNTL__MAX_IDLE_CLK__SHIFT));
/* ACPI mode */
OUTPLL( pllPLL_PWRMGT_CNTL, INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL);
@@ -3577,21 +3608,20 @@
disp_mis_cntl = INREG(DISP_MISC_CNTL);
disp_mis_cntl &= ~( DISP_MISC_CNTL__SOFT_RESET_GRPH_PP |
- DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP |
- DISP_MISC_CNTL__SOFT_RESET_OV0_PP |
- DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK|
- DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK|
- DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK|
- DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP|
- DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK|
- DISP_MISC_CNTL__SOFT_RESET_LVDS|
- DISP_MISC_CNTL__SOFT_RESET_TMDS|
- DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS|
- DISP_MISC_CNTL__SOFT_RESET_TV);
+ DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP |
+ DISP_MISC_CNTL__SOFT_RESET_OV0_PP |
+ DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK|
+ DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK|
+ DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK|
+ DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP|
+ DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK|
+ DISP_MISC_CNTL__SOFT_RESET_LVDS|
+ DISP_MISC_CNTL__SOFT_RESET_TMDS|
+ DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS|
+ DISP_MISC_CNTL__SOFT_RESET_TV);
OUTREG(DISP_MISC_CNTL, disp_mis_cntl);
-
disp_pwr_man = INREG(DISP_PWR_MAN);
disp_pwr_man &= ~( DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN |
@@ -3806,7 +3836,8 @@
static void radeon_pm_yclk_mclk_sync(struct radeonfb_info *rinfo)
-{ u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
+{
+ u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
mc_chp_io_cntl_a1 = INMC( rinfo, ixMC_CHP_IO_CNTL_A1) & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
mc_chp_io_cntl_b1 = INMC( rinfo, ixMC_CHP_IO_CNTL_B1) & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
@@ -3814,6 +3845,7 @@
OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
+ /* Wassup ? This doesn't seem to be defined, let's hope we are ok this way --BenH */
#ifdef MCLK_YCLK_SYNC_ENABLE
mc_chp_io_cntl_a1 |= (2<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT);
mc_chp_io_cntl_b1 |= (2<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT);
@@ -3827,25 +3859,23 @@
static void radeon_pm_program_mode_reg(struct radeonfb_info *rinfo, u16 value, u8 delay_required)
{
- u32 mem_sdram_mode;
+ u32 mem_sdram_mode;
- mem_sdram_mode = INREG( MEM_SDRAM_MODE_REG);
+ mem_sdram_mode = INREG( MEM_SDRAM_MODE_REG);
- mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK;
- mem_sdram_mode |= (value<<MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT) | MEM_SDRAM_MODE_REG__MEM_CFG_TYPE;
- OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
-
- mem_sdram_mode |= MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
- OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
-
- mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
- OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
+ mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK;
+ mem_sdram_mode |= (value<<MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT) | MEM_SDRAM_MODE_REG__MEM_CFG_TYPE;
+ OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
+
+ mem_sdram_mode |= MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
+ OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
- if(delay_required == 1)
- {
- while( (INREG( MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A | MC_STATUS__MEM_PWRUP_COMPL_B) ) == 0 ) { };
- }
+ mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
+ OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
+ if (delay_required == 1)
+ while( (INREG( MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A | MC_STATUS__MEM_PWRUP_COMPL_B) ) == 0 )
+ { };
}
@@ -3854,117 +3884,114 @@
#define DLL_RESET_DELAY 5
#define DLL_SLEEP_DELAY 1
- u32 DLL_CKO_Value = INPLL(pllMDLL_CKO) | MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOA_RESET;
- u32 DLL_CKA_Value = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP | MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET;
- u32 DLL_CKB_Value = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP | MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET;
-
- // Setting up the DLL range for write
- OUTPLL(pllMDLL_CKO, DLL_CKO_Value);
- OUTPLL(pllMDLL_RDCKA, DLL_CKA_Value);
- OUTPLL(pllMDLL_RDCKB, DLL_CKB_Value);
-
- mdelay( DLL_RESET_DELAY);
-
- // Channel A
-
- // Power Up
- DLL_CKO_Value &= ~(MDLL_CKO__MCKOA_SLEEP );
- OUTPLL(pllMDLL_CKO, DLL_CKO_Value);
- udelay( DLL_SLEEP_DELAY);
-
- DLL_CKO_Value &= ~(MDLL_CKO__MCKOA_RESET );
- OUTPLL(pllMDLL_CKO, DLL_CKO_Value);
- mdelay( DLL_RESET_DELAY);
-
- // Power Up
- DLL_CKA_Value &= ~(MDLL_RDCKA__MRDCKA0_SLEEP );
- OUTPLL(pllMDLL_RDCKA, DLL_CKA_Value);
- mdelay( DLL_SLEEP_DELAY);
-
- DLL_CKA_Value &= ~(MDLL_RDCKA__MRDCKA0_RESET );
- OUTPLL(pllMDLL_RDCKA, DLL_CKA_Value);
- mdelay( DLL_RESET_DELAY);
+ u32 DLL_CKO_Value = INPLL(pllMDLL_CKO) | MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOA_RESET;
+ u32 DLL_CKA_Value = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP | MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET;
+ u32 DLL_CKB_Value = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP | MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET;
+
+ /* Setting up the DLL range for write */
+ OUTPLL(pllMDLL_CKO, DLL_CKO_Value);
+ OUTPLL(pllMDLL_RDCKA, DLL_CKA_Value);
+ OUTPLL(pllMDLL_RDCKB, DLL_CKB_Value);
+
+ mdelay( DLL_RESET_DELAY);
+
+ /* Channel A */
+
+ /* Power Up */
+ DLL_CKO_Value &= ~(MDLL_CKO__MCKOA_SLEEP );
+ OUTPLL(pllMDLL_CKO, DLL_CKO_Value);
+ mdelay( DLL_SLEEP_DELAY);
- // Power Up
- DLL_CKA_Value &= ~(MDLL_RDCKA__MRDCKA1_SLEEP);
- OUTPLL(pllMDLL_RDCKA, DLL_CKA_Value);
- mdelay( DLL_SLEEP_DELAY);
-
- DLL_CKA_Value &= ~(MDLL_RDCKA__MRDCKA1_RESET);
- OUTPLL(pllMDLL_RDCKA, DLL_CKA_Value);
- mdelay( DLL_RESET_DELAY);
-
-
- // Channel B
-
- // Power Up
- DLL_CKO_Value &= ~(MDLL_CKO__MCKOB_SLEEP );
- OUTPLL(pllMDLL_CKO, DLL_CKO_Value);
- mdelay( DLL_SLEEP_DELAY);
+ DLL_CKO_Value &= ~(MDLL_CKO__MCKOA_RESET );
+ OUTPLL(pllMDLL_CKO, DLL_CKO_Value);
+ mdelay( DLL_RESET_DELAY);
+
+ /* Power Up */
+ DLL_CKA_Value &= ~(MDLL_RDCKA__MRDCKA0_SLEEP );
+ OUTPLL(pllMDLL_RDCKA, DLL_CKA_Value);
+ mdelay( DLL_SLEEP_DELAY);
+
+ DLL_CKA_Value &= ~(MDLL_RDCKA__MRDCKA0_RESET );
+ OUTPLL(pllMDLL_RDCKA, DLL_CKA_Value);
+ mdelay( DLL_RESET_DELAY);
+
+ /* Power Up */
+ DLL_CKA_Value &= ~(MDLL_RDCKA__MRDCKA1_SLEEP);
+ OUTPLL(pllMDLL_RDCKA, DLL_CKA_Value);
+ mdelay( DLL_SLEEP_DELAY);
+
+ DLL_CKA_Value &= ~(MDLL_RDCKA__MRDCKA1_RESET);
+ OUTPLL(pllMDLL_RDCKA, DLL_CKA_Value);
+ mdelay( DLL_RESET_DELAY);
+
+
+ /* Channel B */
+
+ /* Power Up */
+ DLL_CKO_Value &= ~(MDLL_CKO__MCKOB_SLEEP );
+ OUTPLL(pllMDLL_CKO, DLL_CKO_Value);
+ mdelay( DLL_SLEEP_DELAY);
- DLL_CKO_Value &= ~(MDLL_CKO__MCKOB_RESET );
- OUTPLL(pllMDLL_CKO, DLL_CKO_Value);
- mdelay( DLL_RESET_DELAY);
-
- // Power Up
- DLL_CKB_Value &= ~(MDLL_RDCKB__MRDCKB0_SLEEP);
- OUTPLL(pllMDLL_RDCKB, DLL_CKB_Value);
- mdelay( DLL_SLEEP_DELAY);
-
- DLL_CKB_Value &= ~(MDLL_RDCKB__MRDCKB0_RESET);
- OUTPLL(pllMDLL_RDCKB, DLL_CKB_Value);
- mdelay( DLL_RESET_DELAY);
-
-
- // Power Up
- DLL_CKB_Value &= ~(MDLL_RDCKB__MRDCKB1_SLEEP);
- OUTPLL(pllMDLL_RDCKB, DLL_CKB_Value);
- mdelay( DLL_SLEEP_DELAY);
-
- DLL_CKB_Value &= ~(MDLL_RDCKB__MRDCKB1_RESET);
- OUTPLL(pllMDLL_RDCKB, DLL_CKB_Value);
- mdelay( DLL_RESET_DELAY);
+ DLL_CKO_Value &= ~(MDLL_CKO__MCKOB_RESET );
+ OUTPLL(pllMDLL_CKO, DLL_CKO_Value);
+ mdelay( DLL_RESET_DELAY);
+
+ /* Power Up */
+ DLL_CKB_Value &= ~(MDLL_RDCKB__MRDCKB0_SLEEP);
+ OUTPLL(pllMDLL_RDCKB, DLL_CKB_Value);
+ mdelay( DLL_SLEEP_DELAY);
+
+ DLL_CKB_Value &= ~(MDLL_RDCKB__MRDCKB0_RESET);
+ OUTPLL(pllMDLL_RDCKB, DLL_CKB_Value);
+ mdelay( DLL_RESET_DELAY);
+
+ /* Power Up */
+ DLL_CKB_Value &= ~(MDLL_RDCKB__MRDCKB1_SLEEP);
+ OUTPLL(pllMDLL_RDCKB, DLL_CKB_Value);
+ mdelay( DLL_SLEEP_DELAY);
+
+ DLL_CKB_Value &= ~(MDLL_RDCKB__MRDCKB1_RESET);
+ OUTPLL(pllMDLL_RDCKB, DLL_CKB_Value);
+ mdelay( DLL_RESET_DELAY);
#undef DLL_RESET_DELAY
#undef DLL_SLEEP_DELAY
-
}
static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo)
{
+ u32 crtcGenCntl, crtcGenCntl2, memRefreshCntl, crtc_more_cntl, fp_gen_cntl, fp2_gen_cntl;
+
+ crtcGenCntl = INREG( CRTC_GEN_CNTL);
+ crtcGenCntl2 = INREG( CRTC2_GEN_CNTL);
- u32 crtcGenCntl, crtcGenCntl2, memRefreshCntl, crtc_more_cntl, fp_gen_cntl, fp2_gen_cntl;
-
- crtcGenCntl = INREG( CRTC_GEN_CNTL);
- crtcGenCntl2 = INREG( CRTC2_GEN_CNTL);
-
- memRefreshCntl = INREG( MEM_REFRESH_CNTL);
- crtc_more_cntl = INREG( CRTC_MORE_CNTL);
- fp_gen_cntl = INREG( FP_GEN_CNTL);
- fp2_gen_cntl = INREG( FP2_GEN_CNTL);
-
+ memRefreshCntl = INREG( MEM_REFRESH_CNTL);
+ crtc_more_cntl = INREG( CRTC_MORE_CNTL);
+ fp_gen_cntl = INREG( FP_GEN_CNTL);
+ fp2_gen_cntl = INREG( FP2_GEN_CNTL);
+
- OUTREG( CRTC_MORE_CNTL, 0);
- OUTREG( FP_GEN_CNTL, 0);
- OUTREG( FP2_GEN_CNTL, 0);
+ OUTREG( CRTC_MORE_CNTL, 0);
+ OUTREG( FP_GEN_CNTL, 0);
+ OUTREG( FP2_GEN_CNTL, 0);
- OUTREG( CRTC_GEN_CNTL, (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) );
- OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) );
+ OUTREG( CRTC_GEN_CNTL, (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) );
+ OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) );
- // Disable refresh
- OUTREG( MEM_REFRESH_CNTL, memRefreshCntl | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
+ /* Disable refresh */
+ OUTREG( MEM_REFRESH_CNTL, memRefreshCntl | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
- // Reset memory
- OUTREG( MEM_SDRAM_MODE_REG, INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); // Init Not Complete
+ /* Reset memory */
+ OUTREG( MEM_SDRAM_MODE_REG,
+ INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); // Init Not Complete
- // DLL
- radeon_pm_enable_dll(rinfo);
+ /* DLL */
+ radeon_pm_enable_dll(rinfo);
// MLCK /YCLK sync
radeon_pm_yclk_mclk_sync(rinfo);
- if ((rinfo->arch == RADEON_M6) || (rinfo->arch == RADEON_M7) || (rinfo->arch == RADEON_M9))
- {
+ if ((rinfo->arch == RADEON_M6) || (rinfo->arch == RADEON_M7) || (rinfo->arch == RADEON_M9)) {
radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
@@ -3972,7 +3999,8 @@
radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
}
- OUTREG( MEM_SDRAM_MODE_REG, INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); // Init Complete
+ OUTREG( MEM_SDRAM_MODE_REG,
+ INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); // Init Complete
OUTREG( MEM_REFRESH_CNTL, memRefreshCntl);
@@ -4008,7 +4036,7 @@
/* Prepare mobility chips for suspend
*/
- if ((rinfo->arch == RADEON_M6) || (rinfo->arch == RADEON_M7) || (rinfo->arch == RADEON_M9) ){
+ if (rinfo->arch == RADEON_M6 || rinfo->arch == RADEON_M7 || rinfo->arch == RADEON_M9) {
/* Program V2CLK */
radeon_pm_program_v2clk(rinfo);
@@ -4043,10 +4071,8 @@
pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0);
mdelay(500);
- dbg_clk = INPLL(1);
-
- /* Do we need that on M7 ? */
- if ((rinfo->arch == RADEON_M6) || (rinfo->arch == RADEON_M7) || (rinfo->arch == RADEON_M9) )
+ /* Reset the SDRAM controller */
+ if (rinfo->arch == RADEON_M6 || rinfo->arch == RADEON_M7 || rinfo->arch == RADEON_M9)
radeon_pm_full_reset_sdram(rinfo);
/* Restore some registers */
@@ -4119,7 +4145,6 @@
radeonfb_blank(0, (struct fb_info *)rinfo);
release_console_sem();
- printk("CLK_PIN_CNTL on wakeup was: %08x\n", dbg_clk);
break;
}
}
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