Re: Bug#100657: sysdeps/powerpc/memset.S optimizations fail on power3 CPUs
>On Wed, Jun 13, 2001 at 12:46:52PM +1000, email@example.com wrote:
>> It has always been a problem, memset(,0,) should take into
>> cacheline size but does not.
>> > If this is the only difference between powerpc and power3, then the
>> > only choice I have is to remove this file for powerpc as a generic
>> > solution (I cannot create two sets of libs for ppc and power3).
>> Ben Herrenschmidt has a fix to export the cacheline size from the kernel
>> using aux entries. Glibc may already have support for this.
>Anything new on this?
I don't know the status of glibc, but since around 2.4.5, the kernel
begun exporting those new AUX table entries:
#define AT_DCACHEBSIZE 19
#define AT_ICACHEBSIZE 20
#define AT_UCACHEBSIZE 21
If AT_UCACHEBSIZE exist and contains a non-zero value, then the I/D
cache is unified and it's block (line) size is that value. If it
contains 0, then AT_DCACHEBSIZE and AT_ICACHEBSIZE will contain the
data and instruction cache line sizes.