Bug#324526: Compiling and linking Verilog simulations with VCS 7.2 does not work after libc6 upgrade
At Mon, 22 Aug 2005 11:52:08 -0400,
Ravi Nanavati wrote:
> After upgrading libc6 (from 2.3.2.ds1-22) to 2.3.5-3 I am no longer able to compile and link Verilog simulations with Synopsys VCS. The problem appears to be missing symbols in libc6. The error messages I get are as follows:
> gcc -o ../simv 5NrI_d.o 5NrIB_d.o KDF7_1_d.o SIM_l.o /tools/vcs7.2.new/vcs7.2/gui/virsim/linux/vcdplus/vcs7_2/libvirsim.a /tools/vcs7.2.new/vcs7.2/linux/lib/libvcsnew.so -ldl -lc -lm -ldl
> /tools/vcs7.2.new/vcs7.2/gui/virsim/linux/vcdplus/vcs7_2/libvirsim.a(vcspli.o): In function `vs_clStrCmpCI(char *, char *)':
> : undefined reference to `__ctype_toupper'
I guess your application is not part of Debian, and it was static
linked. During glibc 2.3.x development, some symbols like __ctype_b
is changed to hidden attribute - so old static linked libraries built
with glibc 2.2.x does not work on 2.3.x. In sarge, we introduce
workaround code, so your application worked OK. But most other
distros already dropped such local modification nowadays. For that
reason, we decided to drop supporting such old static linked
applications/libraries from etch.
If you want to enable it again, please recompile debian glibc package
and install it locally, with removing the first # character at the
following line in debian/patches/00list:
#glibc23-ctype-compat # g: untilsarge
Note that I don't test this patch is still applicable.
I'll close this report by writing about this transition to the
appropriate place (ex: README.Debian or FAQ).