Bug#539883: ITP: covered -- Verilog code coverage analysis tool
Package: wnpp
Severity: wishlist
Owner: "أحمد المحمودي" <aelmahmoudy@users.sourceforge.net>
* Package name : covered
Version : 0.7.5
Upstream Author : Trevor Williams <phase1geo@gmail.com>
* URL : http://covered.sourceforge.net/
* License : GPL-2+
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
Programming Lang: C, Tcl
Description : Verilog code coverage analysis tool
Covered is a Verilog code coverage utility that reads in a Verilog design and
a generated VCD/LXT dumpfile from that design and generates a coverage file
that can be merged with other coverage files or used to create a coverage
report. Covered also contains the GUI coverage report utility that reads in a
coverage file to allow interactive coverage discovery. Areas of coverage
measured by Covered are: line, toggle, memory, combinational logic, FSM
state/state-transition and assertion coverage.
-- System Information:
Debian Release: 5.0
APT prefers jaunty-updates
APT policy: (500, 'jaunty-updates'), (500, 'jaunty-security'), (500, 'jaunty-proposed'), (500, 'jaunty-backports'), (500, 'jaunty')
Architecture: i386 (i686)
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