Re: localtalk, was Re: pcmcia ethernet card support for m68k?
On Thu, 13 Aug 2020, Michael Schmitz wrote:
> Am 13.08.2020 um 12:58 schrieb Finn Thain:
> > On Wed, 12 Aug 2020, Michael Schmitz wrote:
> >
> > >
> > > The bit about bus delay should be possible to figure out from timing
> > > access to the SCC data port and compare to RAM access. That might
> > > already decide the issue.
> > >
> >
> > The Guide to Macintosh Family Hardware says that SCC accesses are
> > paced by the GLUE logic.
> >
> > "The SCC requires 2.2 uS between accesses for its intemal lines to
> > stabilize; in the case of back-to-back accesses to the SCC, the
> > GLUE holds off the second access for that amount of time."
>
> Right, it now comes back to me at last - this is what we had used on the
> Atari and VME SCC serial drivers (no need for that with glue logic
> though):
>
> #define scc_reg_delay() \
> do { \
> if (MACH_IS_MVME16x || MACH_IS_BVME6000 || MACH_IS_MVME147) \
> __asm__ __volatile__ ( " nop; nop"); \
> else if (MACH_IS_ATARI) \
> __asm__ __volatile__ ( "tstb %0" : : "g" (*_scc_del) : "cc" );\
> } while (0)
>
>
> The tstb takes around 600 ns. Is the Mac SCC clocked slower than the
> Atari one (8 MHz)?
>
PCLK runs at 3.6864 MHz which means a cycle takes 271 ns. The SCC Users
Manual says, "recovery time is four PCLK cycles (AC Spec #49), measured
from the falling edge of /RD or /WR in the case of a read or write of any
register." That's 1.1 us. I don't know why Apple says 2.2 us but it's
probably academic.
>
> >
> > That's 454545 accesses per second (peak).
> >
>
> Many SCC operations need two accesses ... can the data register be read
> directly on the Mac SCC, or does it need a control register write first?
>
To read the same register again and again, surely you wouldn't have to
write to the register pointer more than once.
> Polling for the entire packet might really be the only way.
>
The data rate is fixed at 230 kB/s so there are only a hundred or so
processor cycles between bytes. Even if there are a few bytes in the
buffer then you probably only have 500 cycles on a fast machine.
If polling is too inefficient then we need to use the DMA controller or
the SCC IOP (on machines that have them).
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