Re: New Amiga drivers coming for Linux 4.18

[Michael Schmitz <schmitzmic@gmail.com>]

Hi Finn,

Am 21.04.2018 um 11:49 schrieb Finn Thain:
> On Fri, 20 Apr 2018, Michael Schmitz wrote:
> 
>>
>> Looking at oktakon_io.S from the 2.16 series, it's using an exception
>> table similar to the Mac PDMA code (the main difference is that the Mac
>> PDMA has the transfer loop unrolled).
> 
> Yes, it seems so.
> 
>> So it would appear the PDMA logic on the Oktagon board can raise a bus 
>> fault to signal transfer errors.
>>
> 
> I think the comments and transfer loops in oktagon_esp.c refute this 
> interpretation.
> 
> On Macs (at least) the PDMA bus fault is not a transfer error, it is a 
> handshaking/pacing mechanism.

I shouldn't have said 'transfer error' - the comments suggest a bus
error is encountered once the processor attempts to transfer additional
bytes after the ESP has ended DMA mode.

> I think that's an important distinction (especially after having tried and 
> failed to get bus_error030() fixed).
> 
> Recall that the scsi target always controls the transfer, not the 
> initiator. Naturally scsi targets care not at all about processor bus 
> timing, and naturally the processor cares not at all about ESP DMA 
> signals.
> 
> Hence the need for special handshaking logic. Bus faults would appear to 
> be inevitable and normal occurrences during transfers.

Yes, that's what I understood. Even though we expect to take an
end-of-DMA interrupt, there is no easy way to break out of the PDMA
transfer loop upon seeing that interrupt (unless we play tricks with the
stack frame - BSD does that AFAIR). Relying on some glue logic to raise
a bus error is the next best thing.

No idea how the target reacts to data transfer between processor and ESP
stalling by interrupt processing - I'd expect the ESP handshake to the
target to stall as well, and should the target give up and change phase
we'd get a bus error on the processor resuming transfer. Maybe this
aspect differs with Mac PDMA.

Am I missing something else here?

> (Alternatively, the PDMA logic can buffer the transfer instead, which is 
> the approach used by 53C400 chips. In this case bus errors never arise.)

I don't think the Oktago PDMA logic does that - bus errors are
definitely expected as a matter of course.

Cheers,

	Michael