Re: PowerPC port for the e500 core
* Olof Johansson | 2009-02-25 14:22:51 [-0600]:
>Hi,
Hi,
>On Tue, Feb 24, 2009 at 03:16:02PM +0100, Sebastian Andrzej Siewior wrote:
>> Hello PowerPC team,
>>
>> I have a Lenny snapshot of a new Debian architecture called gnuspe
>> located at [0]. I haven't announced it anywhere (until now). It is
>> called gnuspe because the gcc triplet is powerpc-linux-gnuspe-. This
>> port is for all PowerPCs which have an E500 core [1]. The main important
>> differences between PowerPC and this one are:
>
>Are you building userspace with SPE instructions enabled, or are you
>using only the base power ISA for the binaries?
SPE enabled.
>> - the "normal" FPU unit is not present. Instead the APU offers float
>> point operations. This is _not_ SW-emulation it is HW support but
>> different at the assembly level. The ABI is also different (there are
>> no dedicated FPU regs).
>> - those opcodes (or some of them) have the same binary representation
>> like AltiVec. The spec forbids AltiVec.
>
>No BookE cores have altivec, besides I don't think the base distro uses
>any altivec since it would not be usable on IBM big iron before power6,
>nor on 603/604 (G3) systems.
SDL/KDE for instance, has AltiVec auto detection via vor v0,v0,v0. If
that one fails the AltiVec support is disabled. Fortunately that one
does not clash with any SPE opcodes. That's what I meant here.
>> - It is not 100% compatible with the PowerPC ISA. An opcode, lwsync,
>> is not supported by the core and raises an invalid opcode exception.
>> This is a core bug.
>
>This is not a core bug per se, but somewhat annoying interpretation of
>the spec by FSL, as far as I know?
The last time I heared Benh talking about, he was refering to it as a
core bug.
>> In the past I used the normal PowerPC port which was sufficient for most
>> things, however it got very slowly once it came to floating point.
>> Starting with gcc 4.2 (I think but starting with Lenny is correct) the
>> gcc starts using the lwsync opcode more frequently and every C++ program
>> is effected via libstdc++ as you can see in #495120. Replacing the opcode
>> in the PowerPc port would cost performance on all other PowerPCs.
>
>Another alternative is to have the kernel rewrite the instruction to be
>a sync instead (which is the expected behaviour on cores not implementing
>lwsync), when the fault is taken.
Yep, that would fix at a price of a fault handler.
>> Now, I wanted to ask if there are more people that could be interrested
>> in this port.
>>
>> Any comments are welcome.
>
>I don't have a personal stake in this, but I think a regular booke port
>(compiled for softfpu and no SPE) would be more valuable, since that
>would also run on IBM/AMCC 4xx CPUs.
You mean a normal PowerPC port with soft float instead of hardfloat?
>-Olof
Sebastian
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